EPM570T144C5 vs EPM570T144C5N 比較

詳細並排比較 EPM570T144C5 由 Intel 與 EPM570T144C5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EPM570T144C5N EPM570T144C5N - MAX II CPLD, 570 LEs, 116 I/O | Intel

EPM570T144C5N - MAX II CPLD, 570 LEs, 116 I/O | Intel

EPM570T144C5N ✓ 啟用中

規格比較

參數 EPM570T144C5 EPM570T144C5N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family MAX II MAX II
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 440 —
Pin-to-Pin Delay (tPD) 5.4 ns —
Maximum Internal Frequency 201.1 MHz —
User I/Os 116 116
Total Package Pins 144 —
封裝 / 外殼 144-TQFP (TQFP-144) —
Core Supply Voltage (VCCINT) [DATA_NEEDED: VCCINT nominal voltage] —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V (multi-voltage I/O supported) —
Configuration Memory On-chip flash (non-volatile, instant-on) —
Programming Interface JTAG (IEEE 1149.1), ISP IEEE 1149.1 JTAG (in-system programmable)
Process Technology 0.18 µm CMOS 0.18 µm 6-layer-metal flash
工作溫度 Commercial (0 °C to +85 °C) 0 °C to +85 °C (commercial, C5 grade)
安裝類型 Surface Mount Surface Mount
RoHS 狀態 Compliant Compliant
Series — MAX II Device
Logic Elements (LEs) — 570
Macrocells — 440
Internal User Flash Memory — 8 Kbit
Global Clocks — 4
Core Voltage (VCCINT) — 1.8 V (typical, internally regulated)
I/O Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage, per bank)
Maximum User I/O Pins — 116
Propagation Delay (tPD) — 5.5 ns (typical, [DATA_NEEDED: exact speed grade])
Maximum Frequency (fMAX) — 201.1 MHz
封裝 — TQFP-144 (20 × 20 mm, 0.5 mm pitch)
Configuration Storage — On-chip non-volatile flash
Supported I/O Standards — LVCMOS, LVTTL, PCI, LVDS, SSTL (per bank VCCIO)
Lead-Free — Yes
MSL 等級 — 3 (per JEDEC J-STD-020)
Design Software — Intel Quartus II (MAX II device support)

資料表與資源

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