EPM570T144C5 - 440-Macrocell MAX II CPLD, 5.4ns, 144-TQFP | Intel
MPN： EPM570T144C5 ✓ 啟用中EPM570T144C5 概覽
A CPLD (Complex Programmable Logic Device) is a non-volatile, flash-backed programmable logic device that sits between simple PLDs (PAL/GAL) and larger FPGAs. The MAX II family uses a look-up-table (LUT) based logic array on a 0.18 µm process and is positioned for low-power, low-cost glue-logic, bus-bridging, I/O expansion, and power-sequencing tasks. Within the broader programmable-logic hierarchy, MAX II belongs to: CPLD → programmable logic device (PLD) → logic IC → integrated circuit → semiconductor.
Key features include 440 macrocells, up to 116 user I/Os (TQFP-144), 5.4 ns pin-to-pin propagation delay, JTAG/IEEE 1149.1 boundary-scan support, ISP (in-system programmability) via JTAG, multi-voltage I/O supporting 1.5 V, 1.8 V, 2.5 V and 3.3 V interfaces, and instant-on (under 1 ms) non-volatile configuration. The device also offers on-chip flash configuration memory, eliminating the need for external boot ROM.
Typical applications include bus-bridging logic (e.g., PCI to local bus), I/O expansion and voltage translation between 3.3 V and 1.8 V domains, power-up sequencing and reset distribution, LED display driving, address decoding in microcontroller systems, and general-purpose glue-logic replacement on industrial and consumer motherboards.
When designing with the EPM570T144C5, observe the 1.8 V VCCINT core supply requirement and use level-shifted I/O banks to interface with mixed-voltage peripherals. The TQFP-144 footprint is shared with several other MAX II and MAX II Z variants, simplifying PCB reuse across density options.
直接替換替代品，適用於 EPM570T144C5 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM570T144C5 （相同外形與佔位） — 差異在於 Programming Interface, Package, Operating Temperature, Process Technology, Maximum User I/O Pins.
EPM570T144C4N
✅ 直接替換聯絡詢價
查看資料表 →EPM570T144C4
✅ 直接替換聯絡詢價
查看資料表 →EPM570T144C3N
✅ 直接替換聯絡詢價
查看資料表 →EPM570T144C3
✅ 直接替換聯絡詢價
查看資料表 →EPM570T144A5N
✅ 直接替換聯絡詢價
查看資料表 →EPM570GT144C5N
✅ 直接替換聯絡詢價
查看資料表 →EPM570GT144C5
✅ 直接替換聯絡詢價
查看資料表 →EPM570GT144C4N
✅ 直接替換聯絡詢價
查看資料表 →EPM570T144C5 最大額定值與電氣特性
| Family | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 440 |
| Pin-to-Pin Delay (tPD) | 5.4 ns |
| Maximum Internal Frequency | 201.1 MHz |
| User I/Os | 116 |
| Total Package Pins | 144 |
| 封裝 / 外殼 | 144-TQFP (TQFP-144) |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V (multi-voltage I/O supported) |
| Configuration Memory | On-chip flash (non-volatile, instant-on) |
| Programming Interface | JTAG (IEEE 1149.1), ISP |
| Process Technology | 0.18 µm CMOS |
| 工作溫度 | Commercial (0 °C to +85 °C) |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
EPM570T144C5 腳位配置
| 腳位 1 | I/O — User I/O pin (bank 1) |
| 腳位 2 | I/O — User I/O pin (bank 1) |
| 腳位 3 | I/O — User I/O pin (bank 1) |
| 腳位 4 | I/O — User I/O pin (bank 1) |
| 腳位 5 | I/O — User I/O pin (bank 1) |
| 腳位 6 | GND — Ground |
| 腳位 7 | I/O — User I/O pin (bank 1) |
| 腳位 8 | I/O — User I/O pin (bank 1) |
| 腳位 9 | VCCIO1 — I/O bank 1 supply voltage |
| 腳位 10 | I/O — User I/O pin (bank 1) |
| 腳位 11 | I/O — User I/O pin (bank 1) |
| 腳位 12 | I/O — User I/O pin (bank 1) |
| 腳位 13 | I/O — User I/O pin (bank 1) |
| 腳位 14 | I/O — User I/O pin (bank 1) |
| 腳位 15 | I/O — User I/O pin (bank 1) |
| 腳位 16 | I/O — User I/O pin (bank 1) |
| 腳位 17 | I/O — User I/O pin (bank 1) |
| 腳位 18 | I/O — User I/O pin (bank 1) |
| 腳位 19 | I/O — User I/O pin (bank 2) |
| 腳位 20 | VCCIO2 — I/O bank 2 supply voltage |
| 腳位 21 | I/O — User I/O pin (bank 2) |
| 腳位 22 | I/O — User I/O pin (bank 2) |
| 腳位 23 | I/O — User I/O pin (bank 2) |
| 腳位 24 | I/O — User I/O pin (bank 2) |
| 腳位 25 | I/O — User I/O pin (bank 2) |
| 腳位 26 | I/O — User I/O pin (bank 2) |
| 腳位 27 | I/O — User I/O pin (bank 2) |
| 腳位 28 | GND — Ground |
| 腳位 29 | I/O — User I/O pin (bank 2) |
| 腳位 30 | I/O — User I/O pin (bank 2) |
| 腳位 31 | I/O — User I/O pin (bank 2) |
| 腳位 32 | I/O — User I/O pin (bank 2) |
| 腳位 33 | I/O — User I/O pin (bank 2) |
| 腳位 34 | I/O — User I/O pin (bank 2) |
| 腳位 35 | I/O — User I/O pin (bank 2) |
| 腳位 36 | I/O — User I/O pin (bank 2) |
| 腳位 37 | VCCIO2 — I/O bank 2 supply voltage |
| 腳位 38 | I/O — User I/O pin (bank 2) |
| 腳位 39 | I/O — User I/O pin (bank 3) |
| 腳位 40 | I/O — User I/O pin (bank 3) |
| 腳位 41 | GND — Ground |
| 腳位 42 | I/O — User I/O pin (bank 3) |
| 腳位 43 | I/O — User I/O pin (bank 3) |
| 腳位 44 | I/O — User I/O pin (bank 3) |
| 腳位 45 | I/O — User I/O pin (bank 3) |
| 腳位 46 | I/O — User I/O pin (bank 3) |
| 腳位 47 | I/O — User I/O pin (bank 3) |
| 腳位 48 | VCCIO3 — I/O bank 3 supply voltage |
| 腳位 49 | I/O — User I/O pin (bank 3) |
| 腳位 50 | I/O — User I/O pin (bank 3) |
| 腳位 51 | I/O — User I/O pin (bank 3) |
| 腳位 52 | I/O — User I/O pin (bank 3) |
| 腳位 53 | I/O — User I/O pin (bank 3) |
| 腳位 54 | I/O — User I/O pin (bank 3) |
| 腳位 55 | I/O — User I/O pin (bank 3) |
| 腳位 56 | GND — Ground |
| 腳位 57 | I/O — User I/O pin (bank 3) |
| 腳位 58 | I/O — User I/O pin (bank 3) |
| 腳位 59 | I/O — User I/O pin (bank 3) |
| 腳位 60 | VCCIO3 — I/O bank 3 supply voltage |
| 腳位 61 | I/O — User I/O pin (bank 4) |
| 腳位 62 | I/O — User I/O pin (bank 4) |
| 腳位 63 | I/O — User I/O pin (bank 4) |
| 腳位 64 | I/O — User I/O pin (bank 4) |
| 腳位 65 | I/O — User I/O pin (bank 4) |
| 腳位 66 | I/O — User I/O pin (bank 4) |
| 腳位 67 | I/O — User I/O pin (bank 4) |
| 腳位 68 | GND — Ground |
| 腳位 69 | I/O — User I/O pin (bank 4) |
| 腳位 70 | VCCIO4 — I/O bank 4 supply voltage |
| 腳位 71 | I/O — User I/O pin (bank 4) |
| 腳位 72 | I/O — User I/O pin (bank 4) |
| 腳位 73 | I/O — User I/O pin (bank 4) |
| 腳位 74 | I/O — User I/O pin (bank 4) |
| 腳位 75 | I/O — User I/O pin (bank 4) |
| 腳位 76 | I/O — User I/O pin (bank 4) |
| 腳位 77 | I/O — User I/O pin (bank 4) |
| 腳位 78 | I/O — User I/O pin (bank 4) |
| 腳位 79 | GND — Ground |
| 腳位 80 | I/O — User I/O pin (bank 4) |
| 腳位 81 | VCCIO4 — I/O bank 4 supply voltage |
| 腳位 82 | I/O — User I/O pin (bank 4) |
| 腳位 83 | I/O — User I/O pin (bank 4) |
| 腳位 84 | I/O — User I/O pin (bank 4) |
| 腳位 85 | I/O — User I/O pin (bank 4) |
| 腳位 86 | I/O — User I/O pin (bank 4) |
| 腳位 87 | I/O — User I/O pin (bank 4) |
| 腳位 88 | TDI — JTAG Test Data In |
| 腳位 89 | TMS — JTAG Test Mode Select |
| 腳位 90 | TCK — JTAG Test Clock |
| 腳位 91 | GND — Ground |
| 腳位 92 | VCCINT — Core supply voltage (1.8 V typical) |
| 腳位 93 | I/O — User I/O pin (bank 4) |
| 腳位 94 | I/O — User I/O pin (bank 4) |
| 腳位 95 | I/O — User I/O pin (bank 4) |
| 腳位 96 | I/O — User I/O pin (bank 4) |
| 腳位 97 | I/O — User I/O pin (bank 1) |
| 腳位 98 | I/O — User I/O pin (bank 1) |
| 腳位 99 | GND — Ground |
| 腳位 100 | I/O — User I/O pin (bank 1) |
| 腳位 101 | I/O — User I/O pin (bank 1) |
| 腳位 102 | VCCIO1 — I/O bank 1 supply voltage |
| 腳位 103 | I/O — User I/O pin (bank 1) |
| 腳位 104 | I/O — User I/O pin (bank 1) |
| 腳位 105 | I/O — User I/O pin (bank 1) |
| 腳位 106 | I/O — User I/O pin (bank 1) |
| 腳位 107 | I/O — User I/O pin (bank 1) |
| 腳位 108 | I/O — User I/O pin (bank 1) |
| 腳位 109 | I/O — User I/O pin (bank 1) |
| 腳位 110 | I/O — User I/O pin (bank 1) |
| 腳位 111 | GND — Ground |
| 腳位 112 | I/O — User I/O pin (bank 1) |
| 腳位 113 | VCCIO1 — I/O bank 1 supply voltage |
| 腳位 114 | I/O — User I/O pin (bank 1) |
| 腳位 115 | I/O — User I/O pin (bank 1) |
| 腳位 116 | I/O — User I/O pin (bank 1) |
| 腳位 117 | I/O — User I/O pin (bank 1) |
| 腳位 118 | I/O — User I/O pin (bank 1) |
| 腳位 119 | I/O — User I/O pin (bank 1) |
| 腳位 120 | I/O — User I/O pin (bank 1) |
| 腳位 121 | I/O — User I/O pin (bank 1) |
| 腳位 122 | GND — Ground |
| 腳位 123 | I/O — User I/O pin (bank 1) |
| 腳位 124 | TDO — JTAG Test Data Out |
| 腳位 125 | I/O — User I/O pin (bank 1) |
| 腳位 126 | VCCINT — Core supply voltage (1.8 V typical) |
| 腳位 127 | I/O — User I/O pin (bank 1) |
| 腳位 128 | I/O — User I/O pin (bank 1) |
| 腳位 129 | I/O — User I/O pin (bank 1) |
| 腳位 130 | I/O — User I/O pin (bank 1) |
| 腳位 131 | I/O — User I/O pin (bank 1) |
| 腳位 132 | I/O — User I/O pin (bank 1) |
| 腳位 133 | I/O — User I/O pin (bank 1) |
| 腳位 134 | GND — Ground |
| 腳位 135 | I/O — User I/O pin (bank 1) |
| 腳位 136 | I/O — User I/O pin (bank 1) |
| 腳位 137 | I/O — User I/O pin (bank 1) |
| 腳位 138 | VCCIO1 — I/O bank 1 supply voltage |
| 腳位 139 | I/O — User I/O pin (bank 1) |
| 腳位 140 | I/O — User I/O pin (bank 1) |
| 腳位 141 | I/O — User I/O pin (bank 1) |
| 腳位 142 | I/O — User I/O pin (bank 1) |
| 腳位 143 | I/O — User I/O pin (bank 1) |
| 腳位 144 | I/O — User I/O pin (bank 1) |
典型應用
EPM570T144C5 適用於 7 應用s: Bus Bridging and Voltage Translation, I/O Expansion for Microcontrollers, Power Sequencing and Reset Distribution, Address Decoding and Chip-Select Generation, Industrial Control and Factory Automation, Consumer Electronics and Display Driving, Communications Equipment Glue Logic.
Bus Bridging and Voltage Translation
The EPM570T144C5 is well-suited to bus-bridging and voltage-level translation between mismatched logic domains because of its 116 user I/Os and multi-voltage I/O bank support (1.5/1.8/2.5/3.3 V). Its 5.4 ns pin-to-pin delay comfortably handles PCI, local-bus, and asynchronous memory interfaces without metastability risk. Placed between a 3.3 V microcontroller and 1.8 V DSP, it acts as a non-volatile, deterministic translator, replacing dozens of 74-series buffers; unlike an FPGA, it has zero boot latency and fits 440 macrocells of glue logic into a single 144-TQFP.
推薦
I/O Expansion for Microcontrollers
The EPM570T144C5 expands GPIO-limited microcontrollers by adding up to 116 user I/Os with JTAG-reprogrammable routing, ideal when the host MCU has insufficient pins for keypads, LEDs, and peripheral strobes. Its 440 macrocells handle per-pin debounce, PWM, and shift-register functions in hardware. Powered from a 2.5 V rail, the device complements 3.3 V MCUs by offloading real-time I/O tasks with deterministic 5.4 ns latency, freeing the MCU CPU for higher-level application code.
推薦
Power Sequencing and Reset Distribution
The EPM570T144C5 generates and distributes multi-rail power-up/power-down sequencing for systems with strict rail-order requirements (e.g., processors requiring core-before-I/O). Its non-volatile flash configuration boots in under 1 ms, far faster than any FPGA, and its 440 macrocells implement delay chains, watchdog timers, and reset-stretch logic. Typical use: sequencing a 1.0 V core, 1.8 V DDR, and 3.3 V I/O with individually programmable delay and fault handling.
推薦
Address Decoding and Chip-Select Generation
The EPM570T144C5 replaces legacy 74-series address-decoder trees with a single 144-TQFP CPLD, generating up to 8-12 qualified chip-selects from a host address bus. Its 5.4 ns tPD ensures glitch-free selects even at 50 MHz bus speeds, and Quartus Prime schematic capture simplifies design entry versus discrete PLDs. With 116 I/Os, designers can decode large memory maps and add interrupt-acknowledge logic on the same device.
推薦
Industrial Control and Factory Automation
The EPM570T144C5 drives digital I/O in PLCs, motor-control interfaces, and factory-automation backplanes thanks to its 116 I/Os and configurable logic blocks for state machines, encoder counters, and safety interlocks. Combined with the industrial-temp variant (EPM570GT144C5N), it operates from -40 °C to +100 °C for factory-floor environments. The 0.18 µm CMOS process gives low quiescent current suitable for always-on industrial controllers.
推薦
Consumer Electronics and Display Driving
The EPM570T144C5 is used in consumer electronics for LED matrix driving, LCD timing control, button scanning, and IR-protocol decoding on cost-sensitive mainboards. Its 116 I/Os multiplex multiple LED rows or LCD segments in time-division, and the 5.4 ns tPD supports standard RGB-interface displays up to 25 MHz pixel clock. The non-volatile flash allows instant-on behavior critical for TV set-top boxes and game consoles.
推薦
Communications Equipment Glue Logic
In routers, switches, and wireless base stations, the EPM570T144C5 acts as glue logic between network processors, PHYs, and SERDES devices, generating frame-sync pulses, LED status indicators, and watchdog strobes. With 440 macrocells it can implement small custom state machines for proprietary PHY bring-up sequences. Multi-voltage I/O support bridges 1.8 V SERDES, 2.5 V PHY, and 3.3 V management interfaces without external level shifters.
推薦
推薦產品摘要
工程參考資料，適用於 EPM570T144C5 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM570T144C4N | EPM570T144C3N | EPM570T144A5N | EPM570GT144C5N | EPM570GT144C5 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 144-TQFP | 144-TQFP - same | 144-TQFP - same | 144-TQFP - same | 144-TQFP - same | 144-TQFP - same |
| Macro Cells | 440 | 440 | 440 | 440 | 440 | 440 |
| Pin-to-Pin Delay (tPD) | 5.4 ns | 4.5 ns (faster) | 3.3 ns (fastest) | 5.4 ns (same) | 5.4 ns (same) | 5.4 ns (same) |
| User I/Os | 116 | 116 | 116 | 116 | 116 | 116 |
| Temperature Grade | Commercial (0 to +85 °C) | Commercial (0 to +85 °C) | Commercial (0 to +85 °C) | Automotive (-40 to +125 °C) | Industrial (-40 to +100 °C) | Industrial (-40 to +100 °C) |
| Lead-Free (Pb-Free) | No (C5 is SnPb; C5N is lead-free) | Yes (C4N suffix) | Yes (C3N suffix) | Yes (A5N suffix) | Yes (C5N suffix) | No |
| Configuration Memory | On-chip flash (non-volatile) | On-chip flash (non-volatile) | On-chip flash (non-volatile) | On-chip flash (non-volatile) | On-chip flash (non-volatile) | On-chip flash (non-volatile) |
主要差異化特點
- Same-family speed-grade options in identical 144-TQFP pinout (對比EPM570T144C4N / EPM570T144C3N)
- Industrial temperature variant (EPM570GT144C5) for harsh environments (對比EPM570T144C5 (commercial))
- Automotive-grade variant (EPM570T144A5N) for AEC-Q100 designs (對比EPM570T144C5 (commercial))
設計說明
Estimated: The EPM570T144C5 requires VCCINT (core, 1.8 V typical) and VCCIO (I/O banks, 1.5/1.8/2.5/3.3 V) rails. Each VCCIO bank can run independently for mixed-voltage I/O. Decouple each VCCIO/VCCINT pin with a 0.1 µF ceramic cap placed within 5 mm of the pin, plus a bulk 10 µF tantalum per supply rail. Power-on ramp must be monotonic; tie unused JTAG pins (TCK, TMS, TDI, TDO) to known states via 10 kΩ pull-ups to VCCIO1 to avoid spurious boundary-scan activity.
Route all four VCCIO bank supplies independently if your design uses mixed voltages (e.g., 3.3 V for bank 1, 1.8 V for bank 2). Place the CPLD close to the JTAG header (≤5 cm) and use a 4-wire TCK/TMS/TDI/TDO topology with TCK ground-shielded to avoid noise-induced programming failures. Leave pin 1 dot indicator visible for assembly orientation. Keep high-speed traces (≥50 MHz) short and impedance-controlled to 50 Ω to preserve signal integrity at the 5.4 ns tPD edge rate.
Do not assume the C5/C4/C3 speed grade suffix is the only ordering code - the trailing "N" denotes lead-free (RoHS) finish, while no "N" indicates SnPb (non-RoHS) finish. RoHS-compliant designs MUST order the C5N variant or equivalent. Also note: VCCINT is NOT the same as VCCIO - confusing these two supplies is a common board bring-up failure that prevents the device from configuring. Confirm with a Quartus Prime IDCODE check before assuming hardware damage.
合規資訊
EPM570T144C5 (without 'N' suffix) is non-RoHS (SnPb finish). For RoHS-compliant designs, order EPM570T144C5N equivalent speed grade - e.g., EPM570T144C4N. AEC-Q100 not applicable to commercial C5 grade; choose EPM570T144A5N for automotive. Compliance values not present in verified web data; lead-free status inferred from suffix convention.
