EPM7096LI68-15 vs EPM7096LC84-15 比較
詳細並排比較 EPM7096LI68-15 由 Intel 與 EPM7096LC84-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7096LI68-15 | EPM7096LC84-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Family | MAX 7000 (second-generation MAX architecture) | MAX 7000 |
| Macrocells | 96 | — |
| Logic Array Blocks (LABs) | 4 | 4 |
| User I/O Pins | 52 | 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Programmable Logic Type | EEPROM-based, in-system programmable (ISP) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG | IEEE Std. 1149.1 JTAG |
| Boundary-Scan Test (BST) | Built-in JTAG BST circuitry | — |
| Output Option | Open-drain output option available | — |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| 封裝 | 68-pin PLCC (J-lead, QCCJ) | — |
| 安裝類型 | Surface Mount (J-lead) | Surface Mount |
| Speed Grade | -15 (15 ns tPD) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Process Technology | CMOS EEPROM | — |
| Series | — | MAX 7000 (second-generation MAX architecture) |
| Macro Cells | — | 96 |
| Usable Gates | — | 1,800 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programmable Type | — | EE PLD (in-system programmable via JTAG) |
| 工作溫度 | — | 0C to +70C (commercial) |
| 封裝 / 外殼 | — | 84-PLCC (J-Lead) |
| Supplier Device Package | — | 84-PLCC (29.31 x 29.31 mm) |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Erase/Program Endurance | — | [DATA_NEEDED: erase/program cycle count] |