EPM9320RC208-10 vs EPM9320RC208-15N 比較
詳細並排比較 EPM9320RC208-10 由 Altera 與 EPM9320RC208-15N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320RC208-10 | EPM9320RC208-15N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| 封裝 | 208-pin RQFP (RC) | 208-pin RQFP (PowerQuad Flat Pack) |
| 工作溫度 | Commercial (0C to +70C) - 'C' suffix | — |
| 供應電壓 | 5 V | 5.0 V |
| Speed Grade | -10 | — |
| Programming Interface | JTAG (ByteBlaster/BitBlaster) | — |
| Non-volatile Configuration | Yes (EPROM/EEPROM based) | — |
| Design Tool Support | MAX+PLUS II, Quartus (legacy) | — |
| RoHS 狀態 | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED: RoHS status] |
| 濕度敏感等級 (MSL) | 3 (168 Hours) | — |
| Lead Time | 1-7 days (per fpgalink listing) | — |
| Macro Cells | — | 320 |
| Flip-Flops | — | 484 |
| Configurable I/O Lines | — | 128 |
| Propagation Delay (tPD) | — | 15 ns |
| 最大時脈頻率 | — | 117.6 MHz |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Configuration Technology | — | CMOS EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Terminal Pitch | — | 0.5 mm |
| 工作溫度範圍 | — | 0C to +70C (commercial) |
| 安裝類型 | — | Surface Mount |
| Packaging | — | Tray |