EPM9560ABC356-10 vs EPM9560GC280-15 比較
詳細並排比較 EPM9560ABC356-10 由 Altera 與 EPM9560GC280-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 Obsolete規格比較
| 參數 | EPM9560ABC356-10 | EPM9560GC280-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Device Family | MAX 9000A | — |
| Product Series | MAX 9000 | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | — |
| Logic Array Blocks (LABs) | 35 | — |
| Maximum User I/Os | 216 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| 供應電壓 | 4.75 V to 5.25 V (5 V nominal) | — |
| Programmability | EEPROM, 5-V In-System Programmable (ISP) | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| 工作溫度 | 0 °C to 70 °C (Commercial) | — |
| 封裝 | 356-LBGA (35 x 35 mm) | — |
| 安裝類型 | Surface Mount | Through-Hole |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | Non-compliant (ceramic CPGA, contains lead) |
| Family | — | MAX 9000 |
| Device Type | — | EE PLD (CMOS EEPROM-based CPLD) |
| Macro Cells | — | 560 |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Technology | — | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Architecture | — | Multiple Array MatriX (MAX) |
| 生命週期狀態 | — | Obsolete (legacy Altera MAX 9000 family) |