EPM9560GC280-20 vs EPM9320GC280-20 比較
詳細並排比較 EPM9560GC280-20 由 Altera 與 EPM9320GC280-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560GC280-20 | EPM9320GC280-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 6000 (approx.) |
| Macrocells | 560 | 320 |
| Maximum User I/O | 212 | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Counter Frequency (max) | 100 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| I/O Voltage | 3.3 V or 5.0 V configurable | — |
| Process Technology | CMOS EEPROM | — |
| 封裝 | 280-pin CPGA (Ceramic Pin Grid Array) | 280-pin Ceramic Pin Grid Array (CPGA) |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | [DATA_NEEDED: operating temperature grade] |
| In-System Programming | Yes, via IEEE 1149.1 JTAG | — |
| 安裝類型 | Through-Hole (CPGA socket) | Through-Hole (PGA socket) |
| RoHS 狀態 | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] | unknown |
| Logic Array Blocks (LABs) | — | 20 (16 macrocells each, typical for MAX 9000) |
| Maximum Operating Frequency | — | 100 MHz (internal counter) |
| Propagation Delay (tpd) | — | 23 ns (approx., -20 speed grade) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (5.0-V ISP via JTAG) |
| JTAG Support | — | IEEE Std. 1149.1 compliant |
| Configuration Memory | — | EEPROM (non-volatile, instant-on) |