EPM9560WC208-20 vs EPM9560RC208-20N 比較
詳細並排比較 EPM9560WC208-20 由 Altera 與 EPM9560RC208-20N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9560WC208-20 - 560-Macrocell CPLD, 23.6ns, PQFP-208 | Intel/Altera
EPM9560WC208-20 Obsolete
規格比較
| 參數 | EPM9560WC208-20 | EPM9560RC208-20N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (EPLD) | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | — |
| User I/O Pins | 149 | 149 |
| Maximum Propagation Delay (tPD) | 23.6 ns | — |
| 封裝 | PQFP-208 (RQFP/WQFP) | 208-pin RQFP (PowerQuad Flat Pack) |
| Process Technology | CMOS, EEPROM-based | — |
| Supply Voltage (VCCINT) | 5 V (typical, see datasheet) | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (multi-voltage I/O) | — |
| In-System Programmability | Yes, JTAG BST (IEEE 1149.1) | Yes, via IEEE Std. 1149.1 JTAG |
| Pin/Package Suffix | W = power PQFP; -20 = 23.6 ns speed grade | — |
| 工作溫度 | Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] | [DATA_NEEDED: operating temperature range] |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] | Lead-free (N suffix) |
| Lead-Free | [DATA_NEEDED] | — |
| 無鹵素 | [DATA_NEEDED] | — |
| MSL 等級 | [DATA_NEEDED] | [DATA_NEEDED: MSL level] |
| Device Family | — | MAX 9000 (EPM9560) |
| Usable Gates | — | 12,000 |
| Propagation Delay (tPD) | — | 20 ns |
| 供應電壓 | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Logic Architecture | — | Multiple Array MatriX (MAX), third-generation CMOS EEPROM |
| Flip-Flops | — | 772 (per EPM9560 series data) |
| Speed Grade | — | -20 (20 ns) |