RTAX2000S-1CGS624V vs RTAX2000SL-1CGS624V 比較

詳細並排比較 RTAX2000S-1CGS624V 由 Microchip Technology 與 RTAX2000SL-1CGS624V 由 Microsemi. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Microchip Technology
RTAX2000S-1CGS624V RTAX2000S-1CGS624V - 2M-Gate Rad-Tolerant FPGA | Microchip

RTAX2000S-1CGS624V - 2M-Gate Rad-Tolerant FPGA | Microchip

RTAX2000S-1CGS624V ✓ 啟用中
Microsemi
RTAX2000SL-1CGS624V RTAX2000SL-1CGS624V - 2M-Gate Rad-Tolerant FPGA | Actel/Microchip

RTAX2000SL-1CGS624V - 2M-Gate Rad-Tolerant FPGA | Actel/Microchip

RTAX2000SL-1CGS624V ✓ 啟用中

規格比較

參數 RTAX2000S-1CGS624V RTAX2000SL-1CGS624V
品牌 Microchip Technology Microsemi
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family RTAX-S Radiation-Tolerant FPGA —
Equivalent System Gates 2,000,000 2000000
Configurable Logic Blocks (CLBs) 21,504 —
Total Logic Cells 32,256 —
ASIC Gate Capacity (companion) 250,000 gates —
Core Supply Voltage (nominal) 1.5 V —
Core Supply Voltage Range 1.425 V to 1.575 V —
Logic Family CMOS —
Speed Grade -1 -1
工作溫度 -55C to +125C [DATA_NEEDED: operating temperature range]
封裝 CG624 Ceramic Column Grid Array (CCGA), 624 balls 624-ball ceramic CGA (CGS624)
安裝類型 Surface Mount Surface Mount
Programming Technology Antifuse (one-time programmable) —
SEU Hardening SEU-hardened registers, immune to single-event upsets —
Embedded Memory Embedded SRAM with built-in FIFO control logic Up to 540 kbits with optional EDAC
Configuration Live at power-up, single-chip (no external config device) One-time programmable (OTP), live at power-up, single chip
RoHS 狀態 [DATA_NEEDED: RoHS status] —
Weight [DATA_NEEDED: package weight] —
Logic Cells (CLBs) — 21504
User I/Os (max, package dependent) — Up to 684
Total Ionizing Dose (TID) — 300 krad (functional), 200 krad (parametric)
SEU Rate — Less than 1E-10 errors per bit-day
Technology — Digital CMOS, antifuse nonvolatile
Quality / Screening Suffix — S (space flow), V suffix qualification level
Core Supply Voltage — [DATA_NEEDED: core supply voltage]
I/O Supply Voltage — [DATA_NEEDED: I/O supply voltage]
Embedded SRAM Features — Built-in FIFO control logic
Clocking — Segmentable clocks, chip-wide highway routing

資料表與資源

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