ADC1005S060TS/C1:1 - 10-bit 60MSPS ADC, 28-SSOP | NXP
MPN： ADC1005S060TS/C1:1 ✓ 啟用中ADC1005S060TS/C1:1 概覽
An ADC (Analog-to-Digital Converter) is a data-acquisition integrated circuit that converts continuous analog signals into discrete digital codes at a sampling rate determined by an external clock. Within the broader signal-chain hierarchy, an ADC sits between analog front-end conditioning (amplifiers, filters) and a downstream DSP, FPGA, or microcontroller. High-speed video-rate ADCs like the ADC1005S060 family are optimized for sub-65 MSPS conversion where 10-bit resolution is sufficient for broadcast, imaging, and instrumentation use cases.
Key differentiating features include a maximum conversion rate of 60 MHz, single-channel single-ended analog input architecture, parallel output interface for easy FPGA/ASIC interfacing, and low power consumption suitable for portable or densely populated video capture cards. Digital I/O is TTL/CMOS compatible, and a low-level sine-wave clock input is also accepted for jitter-sensitive designs.
The ADC1005S060TS/C1:1 uses a flash-style resistance-ladder architecture with internal track-and-hold, providing low-latency conversion suitable for real-time video digitization. The device requires an external reference source to drive the reference ladder; this allows the user to optimize the full-scale range for the application while keeping the internal core compact.
Typical applications include professional video digitizers, digital oscilloscope front ends, IF/baseband sampling in communications receivers, medical imaging front ends, CCD/CIS sensor readout, and industrial machine-vision systems. Designers select this part when 10-bit resolution, 60 MSPS throughput, and a compact 28-SSOP footprint are sufficient and an external reference source is acceptable.
When designing with this ADC, ensure the external reference ladder source is low-noise and well-decoupled, place bypass capacitors close to AVDD/DVDD pins, and route the parallel digital output bus away from the analog input trace to minimize digital feedthrough. The /1 tape-and-reel suffix ('/C1:1') on this part indicates the shipping format and does not change the silicon.
This page synthesizes verified distributor pricing, drop-in pin-compatible alternatives, and practical PCB layout notes that are not aggregated in the manufacturer datasheet alone.
直接替換替代品，適用於 ADC1005S060TS/C1:1 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADC1005S060TS/C1:1 （相同外形與佔位） — 差異在於 Architecture, Operating Temperature Range, Resolution, Package, Sampling Rate (Max).
ADC1005S060TS/C1,1
✅ 直接替換📋 參考替代品（不在目錄中）
ADC1005S060TS-C18
✅ 直接替換📋 參考替代品（不在目錄中）
ADC1004S050TS
✅ 直接替換📋 參考替代品（不在目錄中）
ADC1004S040TS
✅ 直接替換📋 參考替代品（不在目錄中）
ADC1004S030TS
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ADC1003S050TS/C1
✅ 直接替換聯絡詢價
查看資料表 →ADC1003S030TS/C1
✅ 直接替換聯絡詢價
查看資料表 →ADC1005S060TS/C1:1 最大額定值與電氣特性
| 解析度 | 10 bit |
| Number of Channels | 1 |
| Sampling Rate (Max) | 60 MSPS |
| Architecture | Resistance Ladder (Flash-style with internal T/H) |
| Analog Input Type | Single-ended, single channel |
| Data Interface | Parallel (CMOS/TTL-compatible) |
| Reference Type | External (drives internal reference ladder) |
| 供應電壓 | 5 V (single supply, per datasheet) |
| 工作溫度範圍 | -40 C to +85 C |
| Screening Level | Commercial |
| 封裝 / 外殼 | 28-SSOP (5.30 mm body width) |
| 安裝類型 | Surface Mount |
| Packaging (shipping format) | Tape & Reel ('/C1:1' suffix) |
| Clock Input | TTL/CMOS or low-level sine wave |
| Terminal Form | Gull Wing |
ADC1005S060TS/C1:1 腳位配置
| 腳位 1 | D9 (MSB) — Data output bit 9 (MSB) |
| 腳位 2 | D8 — Data output bit 8 |
| 腳位 3 | D7 — Data output bit 7 |
| 腳位 4 | D6 — Data output bit 6 |
| 腳位 5 | D5 — Data output bit 5 |
| 腳位 6 | D4 — Data output bit 4 |
| 腳位 7 | D3 — Data output bit 3 |
| 腳位 8 | D2 — Data output bit 2 |
| 腳位 9 | D1 — Data output bit 1 |
| 腳位 10 | D0 (LSB) — Data output bit 0 (LSB) |
| 腳位 11 | DGND — Digital ground |
| 腳位 12 | DVDD — Digital supply (5 V) |
| 腳位 13 | /OE — Output enable (active low) |
| 腳位 14 | CLK — Clock input |
| 腳位 15 | AGND — Analog ground |
| 腳位 16 | AVDD — Analog supply (5 V) |
| 腳位 17 | AIN — Analog input |
| 腳位 18 | NC — Not connected (per datasheet) |
| 腳位 19 | REFT — Reference ladder top (external reference drive) |
| 腳位 20 | REFB — Reference ladder bottom (external reference drive) |
| 腳位 21 | NC — Not connected (per datasheet) |
| 腳位 22 | NC — Not connected (per datasheet) |
| 腳位 23 | NC — Not connected (per datasheet) |
| 腳位 24 | NC — Not connected (per datasheet) |
| 腳位 25 | NC — Not connected (per datasheet) |
| 腳位 26 | NC — Not connected (per datasheet) |
| 腳位 27 | NC — Not connected (per datasheet) |
| 腳位 28 | NC — Not connected (per datasheet) |
典型應用
ADC1005S060TS/C1:1 適用於 6 應用s: Professional Video Digitizer, IF / Baseband Sampling in Communication Receivers, Digital Oscilloscope Front End, Medical Imaging Digitizer (Ultrasound / CCD Readout), Industrial Machine Vision Systems, CCD / CIS Sensor Readout Electronics.
Professional Video Digitizer
The ADC1005S060TS/C1:1 is well-suited for SDTV and prosumer video digitizers that require 10-bit resolution at 27 MSPS (4x oversampled NTSC/PAL). Its parallel CMOS/TTL output bus feeds directly into an FPGA frame-grabber or video processor without glue logic. The 28-SSOP package allows dense multi-channel designs on a single video-capture card, and the external reference ladder enables per-board gain calibration. Compared with 8-bit converters, the 10-bit resolution provides roughly 12 dB additional dynamic range for cleaner image capture.
推薦
IF / Baseband Sampling in Communication Receivers
In digital-IF receiver designs, the ADC1005S060TS/C1:1 digitizes intermediate-frequency signals below 30 MHz with sufficient bandwidth for narrowband demodulation. The 60 MSPS sampling rate comfortably places the IF in the second Nyquist zone, allowing software-defined radio architectures. The single-ended analog input is straightforward to drive from a 50-ohm-matched IF amplifier, and the parallel output simplifies connection to a baseband DSP. Designers should pair it with a low-jitter clock to keep SNR within datasheet limits.
推薦
Digital Oscilloscope Front End
The ADC1005S060TS/C1:1 serves as the acquisition front end for low-bandwidth digital oscilloscopes and PC-based instruments. Its 10-bit resolution and 60 MSPS throughput enable 6 MHz real-time analog bandwidth, sufficient for hobbyist and educational scopes. The 28-SSOP surface-mount package simplifies assembly on a 4-layer FR-4 digitizer board. For higher bandwidth designs, two ADCs can be interleaved, but the ADC1005S060TS/C1:1 also works standalone where moderate speed is acceptable.
推薦
Medical Imaging Digitizer (Ultrasound / CCD Readout)
Medical imaging systems such as ultrasound receivers and CCD/CIS sensor readouts use the ADC1005S060TS/C1:1 to digitize low-level analog signals with 10-bit precision. The parallel output bus connects directly to an image-processing FPGA or DSP, reducing latency for real-time diagnostic imaging. The 5 V single-supply operation simplifies power-tree design in portable ultrasound carts. Designers should select a low-noise external reference to maximize effective number of bits (ENOB) for diagnostic accuracy.
推薦
Industrial Machine Vision Systems
Factory automation and machine-vision inspection systems use the ADC1005S060TS/C1:1 to digitize analog line-scan or area-scan camera outputs. Its 10-bit resolution captures grayscale depth sufficient for defect detection on conveyor lines. The 28-SSOP industrial-temperature range (-40 C to +85 C) ensures reliable operation in unheated factory floors. The parallel output feeds directly into an FPGA vision pipeline for high-throughput inspection at thousands of parts per minute.
推薦
CCD / CIS Sensor Readout Electronics
Document scanners and digital copiers use the ADC1005S060TS/C1:1 to digitize CCD or CIS image sensor analog output channels. The 60 MSPS sampling rate supports A4-size 300 dpi color scanning at typical line rates, while 10-bit resolution captures the dynamic range needed for color reconstruction. The 28-SSOP package integrates easily alongside CIS analog front ends in compact scanner heads. External reference ladder drive allows per-channel gain matching for color balance.
推薦
推薦產品摘要
工程參考資料，適用於 ADC1005S060TS/C1:1 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADC1005S060TS/C1,1 | ADC1005S060TS-C18 | ADC1004S050TS | ADC1004S040TS | ADC1003S050TS/C1 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | Renesas Electronics | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 28-SSOP | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Max Sampling Rate | 60 MSPS | 60 MSPS | 60 MSPS | 50 MSPS (-17%) | 40 MSPS (-33%) | 50 MSPS (-17%) |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Data Interface | Parallel CMOS/TTL | Parallel CMOS/TTL | Parallel CMOS/TTL | Parallel CMOS/TTL | Parallel CMOS/TTL | Parallel CMOS/TTL |
| Reference Type | External (ladder driven) | External | External | External | External | External |
| Automotive Grade | No (commercial) | No | Yes (AEC-Q100) | No | No | No |
主要差異化特點
- Highest sample rate in the NXP ADC1005/1004/1003 video-ADC family (對比ADC1003S050TS/C1)
- External reference ladder enables per-design full-scale optimization (對比ADC0804S040TS/C1 (fixed internal reference))
- Commercial screening with -40 C to +85 C operating range covers industrial use (對比ADC1005S060TS-C18 (automotive grade))
設計說明
The ADC1005S060TS/C1:1 has separate analog (AVDD) and digital (DVDD) 5 V supply pins. Decouple each pin with a 100 nF ceramic capacitor placed as close as possible to the IC body, and add a 10 uF bulk tantalum or ceramic capacitor on each rail near the device. Use a ferrite bead or pi-filter between the analog and digital 5 V rails to prevent digital switching noise from coupling into the analog input. Estimated: the typical AVDD current for this ADC family is around 30-40 mA at 60 MSPS, so the ferrite must handle at least 50 mA DC without saturation.
Route the parallel digital output bus (D0-D9) on the opposite side of the PCB from the analog input (AIN) trace to minimize digital-to-analog crosstalk. Place a solid ground plane on layer 2 directly beneath the ADC, and stitch the analog and digital grounds together at a single point near the AGND pin of the IC. Keep the CLK trace short and guarded by ground to limit radiated EMI that can degrade SNR.
The reference ladder requires an external low-noise reference source driven into REFT/REFB. A noisy or unstable reference directly degrades SNR and effective number of bits (ENOB); use a dedicated low-noise reference (such as the ADR01 or REF195) with proper output decoupling. Driving the analog input beyond the reference ladder range causes saturation and harmonic distortion; ensure the input amplifier output common-mode and swing stay within the AVDD/2 +/- REFT window.
合規資訊
Compliance fields not directly stated in the verified distributor data. For automotive-grade requirements, the ADC1005S060TS-C18 variant provides AEC-Q100 qualification. RoHS/REACH status should be confirmed with the manufacturer's product compliance documentation.