ADC1213D080HN/C1/5 - Dual 12-bit 80 MSPS ADC, JESD204A, 56-HVQFN
MPN： ADC1213D080HN/C1/5 ✓ 啟用中ADC1213D080HN/C1/5 概覽
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog input voltages into discrete digital codes at a defined sample rate. Dual-channel ADCs such as the ADC1213D integrate two converters on one substrate, sharing clock, reference, and supply circuits, which lowers system BOM cost and reduces board area versus two discrete ADCs. Dual 12-bit ADCs sit in the hierarchy: ADC -> data acquisition IC -> mixed-signal IC -> semiconductor, and they are typically used for communications baseband, radar, medical imaging, and high-speed test instrumentation.
The key performance features of this converter are 12-bit resolution, 80 MSPS sampling rate per channel, dual simultaneous sampling channels, and a pipelined architecture. According to the manufacturer datasheet, the pipelined topology enables high input bandwidth and low latency per stage. The serial JESD204A-style interface reduces digital I/O pin count, simplifies PCB routing, and supports deterministic multi-device synchronization for beamforming and MIMO applications.
Typical applications include communications receivers (LTE / WCDMA baseband), radar and electronic-warfare signal processing, medical ultrasound front-ends, and high-speed data acquisition cards. When designing with this device, pay close attention to analog input common-mode and differential drive, jitter on the sampling clock, and decoupling of the analog and clock supplies - poor decoupling will visibly degrade SNR and SFDR performance.
直接替換替代品，適用於 ADC1213D080HN/C1/5 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADC1213D080HN/C1/5 （相同外形與佔位） — 差異在於 Package, Input Type, Data Interface, Reference Type, Architecture.
ADC1213D125HN/C1/5
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ADC1213D105HN/C1/5
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ADC1213D065HN/C1/5
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ADC1213D080HN/C1
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ADC1213D080HN/C1:8
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ADC1213D080HN/C1/5 最大額定值與電氣特性
| Number of Bits | 12 |
| Sampling Rate (Per Second) | 80 MSPS |
| Number of Inputs | 2 |
| Input Type | Differential |
| Data Interface | Serial, JESD204A |
| Architecture | Pipelined |
| 封裝 / 外殼 | 56-VQFN Exposed Pad (56-HVQFN, 8x8 mm) |
| 安裝類型 | Surface Mount |
| Packaging | Tape & Reel (TR) |
| 工作溫度 | -40C to +85C (Industrial) |
| Number of Terminals | 56 |
| Terminal Form | No Lead |
| Package Code | HVQCCN |
| RoHS 狀態 | Compliant |
| Speed Grade Family | 65 / 80 / 105 / 125 MSPS |
| Configuration | Dual-channel simultaneous sampling |
ADC1213D080HN/C1/5 hvqccn 腳位配置指南
ADC1213D080HN/C1/5（hvqccn 封裝）的腳位配置。 此類比元件具有輸入、輸出與電源腳位。偏移歸零、補償與致能腳位配置請參閱製造商資料表。適用於訊號調理與放大器電路。
無詳細腳位定義資料： ADC1213D080HN/C1/5.
請參閱 資料表 以查看完整腳位配置。
典型應用
ADC1213D080HN/C1/5 適用於 6 應用s: LTE / WCDMA Baseband Receiver, Radar and Electronic Warfare Signal Processing, Medical Ultrasound Front-End, High-Speed Data Acquisition Cards, Software Defined Radio (SDR), Industrial Vibration and Condition Monitoring.
LTE / WCDMA Baseband Receiver
The ADC1213D080HN/C1/5 is well matched to LTE and WCDMA baseband digitisation where dual I/Q channels require simultaneous 80 MSPS sampling. Its 12-bit resolution provides approximately 70 dB SNR, sufficient for the dynamic range of cellular base stations and small cells. The JESD204A serial interface routes the I/Q data over a single differential lane to an FPGA or SoC, minimising PCB trace count on densely populated radio boards. Designers typically place the ADC behind a differential LNA and SAW filter chain, with a low-jitter clock driving the CLK+/- pins to preserve EVM. As of 2026-10-12, this dual-ADC architecture halves component count versus two discrete single-channel ADCs.
推薦
Radar and Electronic Warfare Signal Processing
The dual-channel simultaneous sampling of the ADC1213D080HN/C1/5 enables matched-channel I/Q capture required in radar and EW receivers. Deterministic latency over the JESD204A link supports phase-coherent beamforming across multiple ADC channels in phased-array antennas. With 80 MSPS per ADC, the input bandwidth extends to approximately 40 MHz (Nyquist), suitable for narrow-band surveillance radar front-ends. The 56-HVQFN package with exposed pad handles thermal dissipation when both channels operate at full rate continuously. As of 2026-10-12, this part remains a popular choice in defense and aerospace applications where deterministic latency is mandatory.
推薦
Medical Ultrasound Front-End
The ADC1213D080HN/C1/5 suits ultrasound front-ends where multiple receive channels must be digitised at moderate sampling rates. At 80 MSPS, the part captures RF echo returns from probes up to approximately 40 MHz, covering general-purpose ultrasound imaging. The 12-bit resolution delivers the dynamic range needed for B-mode imaging, while the dual-channel architecture reduces board area in 32- to 128-channel receiver arrays. As of 2026-10-12, the JESD204A interface simplifies routing on the dense multi-channel array boards typical of cart-based and handheld ultrasound designs.
推薦
High-Speed Data Acquisition Cards
The ADC1213D080HN/C1/5 fits PCIe-based data acquisition cards and PXI modules where dual-channel 80 MSPS capture is required. The serial JESD204A interface simplifies routing across the card to the host FPGA or processor, while the 56-HVQFN 8x8 mm package keeps the analog front-end footprint compact. 12-bit resolution supports general-purpose digitiser use cases including vibration analysis, RF recorders, and transient capture. As of 2026-10-12, this converter remains a cost-effective option for mid-bandwidth instrumentation versus 14- or 16-bit parts.
推薦
Software Defined Radio (SDR)
The dual-channel simultaneous sampling of the ADC1213D080HN/C1/5 enables direct-conversion SDR architectures capturing I/Q baseband from a quadrature demodulator. At 80 MSPS, the part digitises channels up to approximately 40 MHz instantaneous bandwidth, suitable for narrow-band HF/VHF/UHF receivers and amateur radio transceivers. The JESD204A interface mates to Zynq or similar SoCs for in-FPGA signal processing. As of 2026-10-12, this converter is a popular mid-tier choice in commercial and amateur SDR platforms requiring low pin count.
推薦
Industrial Vibration and Condition Monitoring
The ADC1213D080HN/C1/5 is suitable for industrial condition monitoring systems that capture vibration signatures from rotating machinery. Dual channels allow simultaneous capture from paired accelerometers for differential measurements, while 80 MSPS provides ample oversampling of mechanical vibration spectra typically below 20 kHz. The industrial temperature grade (-40C to +85C) handles harsh factory environments. As of 2026-10-12, the low pin-count serial interface also simplifies intrinsically-safe enclosure design.
推薦
推薦產品摘要
工程參考資料，適用於 ADC1213D080HN/C1/5 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADC1213D125HN/C1/5 | ADC1213D105HN/C1/5 | ADC1213D065HN/C1/5 | ADC1213D080HN/C1 | ADC1213D080HN/C1:8 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 56-HVQFN (8x8 mm) | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same |
| Sampling Rate | 80 MSPS | 125 MSPS | 105 MSPS | 65 MSPS | 80 MSPS | 80 MSPS |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Interface | JESD204A (serial) | JESD204A (serial) | JESD204A (serial) | JESD204A (serial) | JESD204A (serial) | JESD204A (serial) |
| Packaging Form | Tape & Reel | Tape & Reel | Tape & Reel | Tape & Reel | Tube | Tape & Reel (reel orientation) |
主要差異化特點
- JESD204A serial interface reduces digital pin count (對比AD9268XCPZ-125)
- Dual simultaneous sampling channels in single package (對比Single-channel 12-bit 80 MSPS ADCs)
- Industrial temperature grade as standard (對比Commercial-grade competing ADCs)
設計說明
Route the analog inputs (AIN+/-) as a 100-ohm differential pair with characteristic impedance control, keeping the trace length below 25 mm and isolating them from digital outputs. Place the differential input amplifier (such as an ADA4937) within 10 mm of the ADC inputs to preserve SNR at 80 MSPS. The exposed pad of the 56-HVQFN must be soldered to a continuous ground plane stitched with multiple vias to minimise thermal resistance and provide a low-impedance return path for the analog front-end.
Driving the analog inputs single-ended instead of differential will significantly degrade SNR and SFDR. Ensure the sampling clock CLK+/- is driven by a low-jitter (<200 fs RMS) source such as a clock conditioner, and decouple VA, VD, and VDR supply pins with separate 0.1 uF and 10 uF capacitors placed as close to the package as possible. Do not share the digital supply return path with the analog supply return - star-ground at the exposed pad to avoid digital noise coupling into the analog front-end.
The JESD204A serial lanes run at multi-gigabit rates and require strict impedance control (typically 100-ohm differential) with length matching within 0.13 mm between P and N traces. Place the AC-coupling capacitors close to the receiver end (FPGA) rather than the ADC end to maintain signal integrity. Reference the JESD204A specification for lane rate configuration, LMFC alignment, and SYSREF handling to ensure deterministic latency across multiple ADC devices.
合規資訊
RoHS and lead-free status confirmed via distributor listings. AEC-Q100 not applicable for industrial-grade ADC. Halogen-free status not explicitly stated in available data.
