EP2SGX90EF35C4NES - Stratix II GX FPGA 90K LEs FBGA-35 | Intel
MPN： EP2SGX90EF35C4NES ✗ 停產EP2SGX90EF35C4NES 概覽
An FPGA (Field-Programmable Gate Array) is a semiconductor device whose logic, interconnect, and I/O behavior are defined post-manufacture by a user-supplied configuration bitstream, enabling hardware re-programmability for prototyping, low-volume production, and ASIC emulation. Stratix II GX devices sit in the high-end tier of the FPGA taxonomy: FPGA -> programmable logic -> logic IC -> integrated circuit -> semiconductor. Compared with mask-programmed ASICs, FPGAs trade cost-per-unit for development-time savings and in-field upgradability; compared with CPLDs, they offer far higher density, embedded memory blocks, DSP blocks, and high-speed transceivers.
Key features include 12 multi-gigabit transceivers (up to 6.375 Gbps per the Stratix II GX architecture), dedicated hardware multipliers (up to 192 18x18 multipliers), embedded memory blocks (M4K/M-RAM/RAM), four embedded PLLs per quadrant, support for external memory interfaces (DDR/DDR2/QDR), and up to 8 phase-aligned transmitter PLLs. The 'EF' suffix designates the enhanced-feature 90K-LE device with full transceiver count, while '35' in the package code refers to the FBGA ball-out family used in the Stratix II GX family.
Typical applications include 10 Gbps Ethernet MAC and XAUI interfaces, PCI Express Gen1 endpoints, Serial RapidIO and HD-SDI video bridging, high-speed serial backplane aggregation, and prototype ASIC replacement for telecom line cards. The combination of high logic density, embedded transceivers, and rich memory resources makes the EP2SGX90 suitable for systems that previously required a discrete PHY plus an FPGA.
When designing with this device, ensure the Quartus II design software (version 13.0 or earlier for legacy support) is used, since the Stratix II GX family predates Intel Quartus Prime's primary support window. PCB layout must respect controlled-impedance differential routing (100 ohm differential for transceivers) and decoupling per Altera's Stratix II GX pin connection guidelines.
直接替換替代品，適用於 EP2SGX90EF35C4NES — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EP2SGX90EF35C4NES （相同外形與佔位） — 差異在於 Package, Logic Elements, RoHS Status, Speed Grade, Operating Temperature.
EP2SGX90EF35C3NES
✅ 直接替換聯絡詢價
查看資料表 →EP2SGX90EF35C5NES
✅ 直接替換聯絡詢價
查看資料表 →EP2SGX90EF1152C4
✅ 直接替換聯絡詢價
查看資料表 →EP2SGX90EF1152C3
✅ 直接替換聯絡詢價
查看資料表 →EP2SGX90EF1152I4
✅ 直接替換聯絡詢價
查看資料表 →EP2SGX90EF1508C4
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查看資料表 →EP2SGX90EF35C4NES 最大額定值與電氣特性
| Family | Stratix II GX |
| Logic Elements | Approximately 90,000 |
| Embedded Memory | Up to 4.5 Mbits (M4K + M-RAM blocks) |
| Transceivers | 12 multi-gigabit transceivers |
| Transceiver Data Rate | Up to 6.375 Gbps |
| Hardware Multipliers | Up to 192 (18x18) |
| Core Voltage | 1.2 V |
| MultiVolt I/O | Supports 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Speed Grade | C4 (commercial-extended) |
| 封裝 | FBGA-35 / 1152-ball BGA family |
| 安裝類型 | Surface Mount (BGA) |
| RoHS 狀態 | Pb-free (N suffix indicates lead-free assembly) |
| Process Technology | 90 nm CMOS |
| PLLs | Up to 8 (4 quadrants) |
| Configuration Method | Serial / Passive parallel / Fast passive parallel |
EP2SGX90EF35C4NES fbga-35 / 1152-ball bga family 腳位配置指南
EP2SGX90EF35C4NES（fbga-35 / 1152-ball bga family 封裝）的腳位配置。 此數位 IC 包含 GPIO、通訊介面（UART、SPI、I2C）與電源腳位。替代腳位功能與配置選項請參閱製造商資料表。對嵌入式系統設計與 PCB 佈局至關重要。
無詳細腳位定義資料： EP2SGX90EF35C4NES.
請參閱 資料表 以查看完整腳位配置。
典型應用
EP2SGX90EF35C4NES 適用於 6 應用s: 10 Gigabit Ethernet MAC / XAUI Aggregation, PCI Express Gen1 Endpoint Card, Serial RapidIO Switch / Bridge, HD-SDI / SDI Video Router, ASIC Prototype / Emulation Platform, High-Speed Serial Backplane Aggregation.
10 Gigabit Ethernet MAC / XAUI Aggregation
The EP2SGX90EF35C4NES integrates 12 multi-gigabit transceivers capable of up to 6.375 Gbps, which is sufficient to implement four XAUI lanes (4 x 3.125 Gbps) plus auxiliary ports for 10 Gigabit Ethernet MAC aggregation in a single device. Its 90K logic elements and ~4.5 Mbits of embedded RAM provide the fabric for custom MAC, oversubscription buffering, and statistics counters. The device's dedicated transceiver PLLs and clock data recovery (CDR) eliminate external PHY cost on line-card designs, while 192 18x18 hardware multipliers accelerate per-flow hashing. PCB layout must observe 100 ohm differential impedance and length matching within the Stratix II GX handbook guidelines.
推薦
PCI Express Gen1 Endpoint Card
The EP2SGX90EF35C4NES supports PCI Express Gen1 x4 (4 lanes at 2.5 Gbps per lane) using its built-in transceivers and the Altera PCIe hard IP block, providing a complete endpoint for workstation add-in cards, RAID controllers, or data acquisition modules. The 90K LEs handle the PCIe transaction layer, DMA engine, and user application logic, while the 4.5 Mbits of embedded memory serve as descriptor rings and packet buffers. The C4 speed grade supports the 250 MHz internal clock typically required for Gen1 applications, and the FBGA-35 package offers adequate ball count for x4 lanes plus standard PCIe reference clock and sideband signals.
推薦
Serial RapidIO Switch / Bridge
The 12 transceivers in the EP2SGX90EF35C4NES enable a 4x Serial RapidIO (SRIO) port implementation at 3.125 Gbps per lane, plus additional SRIO lanes for fabric expansion in DSP cluster or wireless baseband systems. The 90K logic elements are sufficient for SRIO logical, transport, and physical layer processing, message routing, and doorbell handling. Embedded memory blocks are well suited to descriptor and payload buffering, while the 192 hardware multipliers accelerate any on-board DSP preprocessing. Designers should consult the Altera SRIO MegaCore function documentation for PHY and logical layer IP targeting the Stratix II GX family.
推薦
HD-SDI / SDI Video Router
The EP2SGX90EF35C4NES supports multiple HD-SDI (1.485 Gbps) or 3G-SDI (2.97 Gbps) channels simultaneously using its multi-gigabit transceivers, with the 90K logic elements implementing crosspoint switching, embedding/de-embedding, and audio mux logic. The C4 speed grade comfortably supports HD-SDI rates and the FBGA-35 package provides enough user I/O for downstream parallel video processing ASICs or FPGAs. Altera's SDI MegaCore IP targets the Stratix II GX transceivers directly. Broadcast router chassis based on this device are common in studio and outside-broadcast infrastructure.
推薦
ASIC Prototype / Emulation Platform
The 90K logic elements and 4.5 Mbits of embedded memory in the EP2SGX90EF35C4NES are well suited to ASIC and ASSP prototyping, where design teams partition a multi-million-gate ASIC across multiple FPGAs and verify functionality, performance, and software before tape-out. Multi-gigabit transceivers enable high-throughput chip-to-chip bridging between FPGAs in a multi-FPGA emulation rack, supporting gigabit-level partitioned debugging bandwidth. Quartus II design software supports incremental compile and LogicLock regions to streamline the ASIC-to-FPGA mapping flow.
推薦
High-Speed Serial Backplane Aggregation
The EP2SGX90EF35C4NES with 12 transceivers aggregating at 3.125-6.375 Gbps serves as a backplane aggregation FPGA in ATCA, microTCA, or proprietary chassis systems, where multiple lower-speed serial lanes are combined into higher-speed uplinks. Its 90K logic elements handle SERDES mapping, link training, and traffic management, while the embedded memory buffers bursts. Industrial temperature variants (e.g., EP2SGX90EF1152I4) are available for harsh-environment backplane applications, sharing the same die for thermal and signal-integrity design reuse.
推薦
推薦產品摘要
工程參考資料，適用於 EP2SGX90EF35C4NES — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EP2SGX90EF35C3NES | EP2SGX90EF35C5NES | EP2SGX90EF1152C4 | EP2SGX90EF1152C3 | EP2SGX90EF1152I4 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | FBGA-35 (1152-ball) | FBGA-35 (1152-ball) - same | FBGA-35 (1152-ball) - same | FBGA / 1152-ball - same ball count, alternative pinout | FBGA / 1152-ball - same ball count | FBGA / 1152-ball - same ball count |
| Logic Elements | 90,000 | 90,000 | 90,000 | 90,000 | 90,000 | 90,000 |
| Transceivers | 12 | 12 | 12 | 12 | 12 | 12 |
| Speed Grade | C4 | C3 (faster) | C5 (slower) | C4 (same) | C3 (faster) | C4 (same) |
| Temperature Grade | Commercial Extended | Commercial Extended | Commercial Extended | Commercial Extended | Commercial Extended | Industrial (-40C to +100C) |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Embedded Memory | 4.5 Mbits | 4.5 Mbits | 4.5 Mbits | 4.5 Mbits | 4.5 Mbits | 4.5 Mbits |
主要差異化特點
- Pin-compatible C3 speed grade for higher Fmax (對比EP2SGX90EF35C3NES)
- Industrial temperature option with same die (對比EP2SGX90EF1152I4)
- 12 transceivers integrated vs. external PHY solutions (對比Discrete transceiver + smaller FPGA design)
設計說明
The FBGA-35 (1152-ball) Stratix II GX package requires a 1.0 mm or finer ball pitch PCB with microvia stack-up. Per Altera's Stratix II GX pin connection guidelines, dedicate continuous ground and power planes beneath the BGA and use a 4-6 layer stack-up with 50 ohm single-ended and 100 ohm differential controlled impedance for the 12 transceiver channels. Estimated: total BGA footprint is ~35x35 mm, requiring ~10:1 aspect-ratio microvia capability; high-volume designs should validate BGA warpage with the manufacturer's MSL handling profile (JEDEC J-STD-020).
The EP2SGX90EF35C4NES can dissipate 5-10 W typical in transceiver-active designs, requiring thermal vias under the BGA's exposed thermal balls and adequate chassis airflow. Estimated: at 8 W dissipation in a FBGA with theta-JA ~10 C/W (with thermal vias and 4-layer PCB), the junction temperature rise is ~80 C above ambient - sufficient thermal margin exists for the commercial-extended 85 C rating, but enclosure airflow should be verified at the system level.
The Stratix II GX family requires Altera Quartus II design software (legacy version 13.0 or earlier, since Intel Quartus Prime no longer supports Stratix II). Configuration via legacy AS, PS, or FPP modes requires a compatible EPCS or EPCQ configuration device. Power-on sequencing for the 1.2 V core and the MultiVolt I/O banks must follow Altera's POR guidelines - failure to sequence properly can cause latch-up. Transceiver reference clocks must be within +/-50 ppm of the configured rate per the Stratix II GX handbook.
合規資訊
The 'N' suffix in EP2SGX90EF35C4NES indicates lead-free / Pb-free assembly per Altera's 2005+ lead-free product roadmap. RoHS compliance is implied by the lead-free finish. REACH, halogen-free, and conflict-minerals certifications were not found in the verified 2026-09-09 web data; consult Intel's product compliance portal for formal documentation.
