EPC2LC120 - PLCC-120 Altera FPGA Config Device | Intel
MPN： EPC2LC120 ✗ 停產EPC2LC120 概覽
A configuration device is a non-volatile memory IC that holds the FPGA configuration bitstream and presents it to the target FPGA at power-on via a structured handshake protocol (typically Altera's FPP or PS scheme). It sits in the FPGA boot hierarchy as the third tier: below JTAG-direct programming and below processor-driven configuration, but above the absent-on-board-boot-PROM option. EPC2 devices are specifically tailored to Altera's proprietary configuration state machine, exposing CONF_DONE, nSTATUS, nCONFIG, and DCLK signals that handshake with the FPGA. Unlike generic SPI flash, the EPC2 family integrates compression, error-checking, and remote update logic.
Key features of the EPC2LC120 include 2 Mbit (approximately 250 Kbyte) configuration storage density, byte-wide or serial configuration data width selectable per design, 3.3V single-supply operation, JTAG IEEE 1149.1 boundary-scan compliance for in-system programming, and a small footprint PLCC-120 package with socket compatibility for field replacement. The device supports multi-device configuration chains, enabling a single EPC2 to program multiple FPGAs in parallel or serial mode depending on the system architecture.
From an architectural standpoint, the EPC2LC120 uses an embedded CMOS non-volatile memory cell array with on-chip charge pumps and a serial/parallel configuration controller. The integrated controller handles Altera's proprietary configuration handshaking and supports optional compression (up to 2:1) of the stored bitstream, effectively doubling usable density. The device also supports remote update via the Altera multi-mode configuration protocol, allowing firmware revisions over JTAG without removing the device from the board.
Typical applications include legacy Altera FLEX 10K/ACEX 1K/APEX 20K series FPGA configuration, industrial control boards with field-upgradable logic, military and aerospace systems using older Altera silicon, and prototyping platforms where the configuration memory must be hot-swappable. The PLCC-120 socket makes it well suited to engineering development environments where configuration files change frequently.
When designing with the EPC2LC120, ensure the JTAG chain order is correct so that the EPC2 is programmed as a slave device alongside the FPGA. Decoupling caps (0.1uF ceramic placed adjacent to each VCC pin) are recommended to handle the in-system programming write currents. Confirm the FPGA configuration mode (FPP/PS/PPA) matches the EPC2 data-width setting in the Quartus configuration editor.
直接替換替代品，適用於 EPC2LC120 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPC2LC120 （相同外形與佔位） — 差異在於 Package, Memory Type, Mounting Type, Interface, Operating Temperature.
EPC2L120
✅ 直接替換聯絡詢價
查看資料表 →EPC1LC120
✅ 直接替換聯絡詢價
查看資料表 →EPC144LC20
✅ 直接替換聯絡詢價
查看資料表 →EPC2LC120 最大額定值與電氣特性
| 功能 | FPGA Configuration Memory Device |
| Memory Density | 2 Mbit |
| Compatible FPGA Families | FLEX, ACEX, APEX, Mercury (Altera) |
| 封裝 | PLCC-120 |
| 腳位數 | 120 |
| 供應電壓 | 3.3 V |
| Programming Interface | JTAG IEEE 1149.1 |
| Configuration Modes | PS (serial), PPA (parallel), multi-device daisy chain |
| 安裝類型 | Surface Mount / Socket |
| Data Compression Support | Yes (Altera proprietary, up to 2:1) |
| Remote Update Support | Yes (via JTAG multi-mode protocol) |
EPC2LC120 plcc-120 腳位配置指南
EPC2LC120（plcc-120 封裝）的腳位配置。 此數位 IC 包含 GPIO、通訊介面（UART、SPI、I2C）與電源腳位。替代腳位功能與配置選項請參閱製造商資料表。對嵌入式系統設計與 PCB 佈局至關重要。
無詳細腳位定義資料： EPC2LC120.
請參閱 資料表 以查看完整腳位配置。
典型應用
EPC2LC120 適用於 6 應用s: Legacy FLEX 10K FPGA Configuration, ACEX 1K Industrial Controller, APEX 20K DSP Board Configuration, Mercury FPGA High-Speed Signal Processor, Multi-Device Daisy-Chain Configuration, Field-Upgradeable Legacy Avionics.
Legacy FLEX 10K FPGA Configuration
The EPC2LC120 is the standard configuration memory for Altera FLEX 10K series FPGAs such as the EPF10K100 and EPF10K250. At power-on the EPC2 presents the 2 Mbit bitstream over the parallel PPA bus (or serial PS mode) and the FLEX 10K device handshakes via CONF_DONE/nSTATUS/nCONFIG. Engineers should keep JTAG chain ordering such that the EPC2 programs first as a slave device. The 3.3V single-supply rail matches the FLEX 10K VCCINT domain, eliminating an extra LDO. Quartus software generates the .rbf or .hex file programmed into the EPC2.
推薦
ACEX 1K Industrial Controller
The EPC2LC120 stores the configuration bitstream for Altera ACEX 1K FPGAs (e.g., EP1K30, EP1K100) used widely in industrial control boards where hot-swappable upgrades are needed. The PLCC-120 socket lets field technicians replace the configuration device without desoldering, which simplifies firmware revision service. The EPC2 compression feature effectively doubles usable density, accommodating ACEX designs that approach the 2 Mbit ceiling. Decoupling caps (0.1uF ceramic adjacent to each VCC pin) are recommended for the in-system programming write-current spikes.
推薦
APEX 20K DSP Board Configuration
APEX 20K and APEX II FPGAs (EP20K200, EP20K400) target DSP and parallel-processing boards. The EPC2LC120's 2 Mbit storage and parallel PPA interface enable fast multi-megabit configuration of these high-density devices in under 50 ms. The remote-update feature lets engineers field-revise APEX firmware via JTAG without removing the EPC2 from the board. Place the EPC2 within 100 mm of the APEX DATA[7:0] and DCLK pins to preserve signal integrity at the 33 MHz configuration clock rate.
推薦
Mercury FPGA High-Speed Signal Processor
Altera Mercury FPGAs (EP1M120, EP1M350) deliver multi-gigabit transceiver capability, and the EPC2LC120 reliably delivers their configuration bitstream at 33 MHz over the parallel bus. The PLCC-120 socket lets board designers swap configuration memory on prototype builds as firmware evolves. Because Mercury boards operate at gigahertz speeds, the EPC2LC120's slow JTAG programming does not affect live signal integrity - programming is done in standby mode. Pair with 10kohm pull-ups on CONF_DONE and nSTATUS to prevent spurious configuration triggers.
推薦
Multi-Device Daisy-Chain Configuration
The EPC2LC120 supports multi-device daisy-chaining so a single EPC2 can configure multiple Altera FPGAs in serial mode by cascading the CONF_DONE and DCLK lines through the chain. This is common on boards that pair a FLEX 10K control FPGA with an ACEX 1K co-processor. Quartus software generates the merged bitstream that the EPC2LC120 stores; the order in which each FPGA receives the bitstream is configured in the .sof programming file. Designers must verify that the total bitstream fits within the 2 Mbit density after Altera's compression.
推薦
Field-Upgradeable Legacy Avionics
Military and aerospace programs built on FLEX 10K and APEX 20K FPGAs continue to operate decades after deployment, and the EPC2LC120 supports field firmware revisions via JTAG without removing the FPGA. The PLCC-120 socket allows ground crews to physically swap the EPC2 if a configuration memory fault is diagnosed. The EPC2 remote-update feature integrates with on-board test equipment to verify the new bitstream before committing. Engineers must consider obsolescence risk for new avionics programs and plan a migration path to current Intel FPGAs.
推薦
推薦產品摘要
工程參考資料，適用於 EPC2LC120 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPC2L120 | EPC1LC120 | EPC144LC20 |
|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | PLCC-120 | PLCC-120 | PLCC-120 | PLCC-20 |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Programming Interface | JTAG IEEE 1149.1 | JTAG | JTAG | JTAG |
| FPGA Family Support | FLEX/ACEX/APEX/Mercury | FLEX/ACEX/APEX/Mercury | FLEX/ACEX | FLEX/ACEX |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
主要差異化特點
- Only 2 Mbit member of EPC2 family in PLCC-120 footprint (對比EPC1LC120)
- Integrated bitstream compression (對比EPC1LC120)
- Remote-update capability (對比EPC144LC20)
設計說明
Place the EPC2LC120 within 100 mm of the target FPGA's DATA[7:0] and DCLK pins. Route DCLK as a 50-ohm controlled-impedance trace and place a 33-ohm series damping resistor at the FPGA end if the trace exceeds 50 mm. Keep JTAG TCK/TMS/TDO/TDI traces away from switching power and clock signals to prevent programming errors.
Decouple each VCC pin of the EPC2LC120 with a 0.1uF ceramic capacitor placed within 3 mm of the pin. Add a single 10uF tantalum or ceramic bulk capacitor near the device to handle in-system programming write-current transients, which can briefly reach 50 mA per VCC pin. Maintain a clean 3.3V rail - ripple above 50 mVpp can cause configuration bitstream errors.
Do NOT use the EPC2LC120 with newer Intel FPGA families (Cyclone, Stratix, Agilex) - their configuration protocol is incompatible and will not configure. Ensure JTAG chain ordering places the EPC2LC120 BEFORE the FPGA in the JTAG chain so that Quartus can program it as a slave device. Verify the configuration mode (PS vs PPA) in Quartus matches the FPGA mode pins MSEL[2:0] strap settings; mismatches prevent configuration startup.
合規資訊
Compliance data not present in the Verified Web Data for this obsolete part. Engineers should request a compliance statement directly from franchised Altera/Intel distributors or the legacy Altera product archive before placing orders for regulated applications.
