EPC2LC22N - 1.6Mb Altera Configuration PROM | PLCC-22
MPN： EPC2LC22N ✗ 停產EPC2LC22N 概覽
A configuration PROM is a non-volatile memory device that holds the FPGA's configuration bitstream. When the FPGA powers up, it reads its configuration data from a configuration PROM (typically via JTAG or a dedicated serial interface). Configuration PROMs belong to the broader category of non-volatile memory ICs and serve as boot memory for SRAM-based FPGAs (which lose their configuration when power is removed). The EPC2 family specifically targets Altera's legacy APEX, Mercury, ACEX, Cyclone, and Stratix FPGAs.
Key features of the EPC2LC22N include in-system programmability via IEEE 1149.1 (JTAG) boundary-scan, cascadable architecture for multi-device configuration chains, and low-power CMOS technology. The device supports Altera's serial configuration protocol and can be cascaded to support arbitrarily large bitstreams. The 2.5V core (LC designation) provides lower power consumption than the 5V and 3.3V variants in the EPC2 family.
The EPC2LC22N uses a 4-pin JTAG interface (TCK, TMS, TDI, TDO) for in-system programming, eliminating the need for a separate PROM programmer. The cascadable design allows multiple EPC2 devices to be chained together to configure FPGAs with bitstreams larger than 1.6 Mbits. The device includes an internal oscillator and timing control, simplifying board design by removing the need for external configuration clock generation.
Typical applications include legacy Altera APEX 20K / APEX II FPGA configuration, ACEX 1K boot memory, Mercury device support, and embedded systems requiring in-field FPGA reconfiguration via JTAG. The PLCC-22 through-hole package is suited for prototyping, legacy board designs, and applications where socketed configuration memory is preferred for field serviceability.
When designing with the EPC2LC22N, ensure the JTAG chain is properly terminated and the FPGA's MSEL pins are set to the correct configuration mode for serial PROM boot. Note that this part is now in legacy status and is replaced in many new designs by newer Cyclone/MAX series FPGAs with built-in flash configuration memory, eliminating the external PROM altogether.
This page synthesizes Intel/Altera datasheet information, distributor pricing, and drop-in compatible EPC2 family alternatives not found in a single manufacturer document, providing practical sourcing guidance for legacy FPGA design maintenance.
直接替換替代品，適用於 EPC2LC22N — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPC2LC22N （相同外形與佔位） — 差異在於 Memory Type, Mounting Type, Interface, Package, Supply Voltage.
EPC2LC22N 最大額定值與電氣特性
| 記憶體類型 | Configuration PROM (non-volatile) |
| 記憶體容量 | 1.6 Mbit |
| 供應電壓 | 2.5 V (LC core) |
| 介面 | Serial configuration / JTAG (IEEE 1149.1) |
| Programmability | In-system programmable (ISP) via JTAG |
| Cascadable | Yes - supports multi-device configuration chains |
| 封裝 | PLCC-22 (Plastic Leaded Chip Carrier) |
| 安裝類型 | Surface Mount / Through Hole socket |
| Configuration Compatibility | Altera APEX, ACEX, Mercury, Cyclone, Stratix series FPGAs |
| JTAG Pins | TCK, TMS, TDI, TDO |
| Internal Oscillator | Yes (built-in configuration timing) |
| Status | Legacy / Obsolete (replaced by flash-based FPGA configuration) |
EPC2LC22N 腳位配置
| 腳位 1 | VCC — Core supply voltage (2.5V LC core) |
| 腳位 2 | GND — Ground |
| 腳位 3 | DATA — Serial data output to FPGA |
| 腳位 4 | DCLK — Configuration clock output |
| 腳位 5 | nCONFIG — Configuration control (input to PROM) |
| 腳位 6 | nSTATUS — Configuration status (output from FPGA) |
| 腳位 7 | CONFIG_DONE — Configuration complete signal |
| 腳位 8 | nCE — Chip enable (active low) |
| 腳位 9 | OE — Output enable |
| 腳位 10 | TMS — JTAG test mode select |
| 腳位 11 | TCK — JTAG test clock |
| 腳位 12 | TDO — JTAG test data output |
| 腳位 13 | TDI — JTAG test data input |
| 腳位 14 | NC — Not connected (per datasheet) |
| 腳位 15 | GND — Ground |
| 腳位 16 | VCC — Core supply voltage (2.5V LC core) |
| 腳位 17 | NC — Not connected (per datasheet) |
| 腳位 18 | NC — Not connected (per datasheet) |
| 腳位 19 | NC — Not connected (per datasheet) |
| 腳位 20 | RESET — Reset input (active low) |
| 腳位 21 | NC — Not connected (per datasheet) |
| 腳位 22 | NC — Not connected (per datasheet) |
典型應用
EPC2LC22N 適用於 6 應用s: Altera APEX 20K Series FPGA Configuration, ACEX 1K FPGA Boot Memory, Mercury Device Configuration Support, Cyclone Series Legacy Configuration, Stratix Configuration Memory, In-Field FPGA Reconfiguration Systems.
Altera APEX 20K Series FPGA Configuration
The EPC2LC22N's 1.6 Mbit non-volatile memory matches the configuration bitstream size of Altera APEX 20K and APEX II FPGAs, providing instant-on boot memory that survives power cycles. According to the EPC2 datasheet, the LC core's 2.5V supply aligns with APEX 20K's auxiliary supply rail, simplifying board power design. The JTAG-based ISP enables field firmware updates without removing the device from its socket - critical for industrial APEX systems still in service.
推薦
ACEX 1K FPGA Boot Memory
The EPC2LC22N serves as boot memory for legacy ACEX 1K FPGAs (EP1K, EP1KA series) with configuration data up to 1.6 Mbit. The cascadable architecture supports multi-device configuration chains for larger ACEX bitstreams exceeding single-PROM capacity. According to Altera configuration guides, the LC core's low power consumption reduces standby draw in ACEX-based embedded systems where thermal envelope is constrained.
推薦
Mercury Device Configuration Support
The EPC2LC22N configures Altera Mercury series FPGAs (EP1M series) used in high-speed communication and signal processing applications. According to the EPC2 datasheet, the JTAG-based ISP allows field upgrades of Mercury bitstreams in deployed telecom and test equipment, extending the service life of legacy infrastructure. The PLCC-22 socketed form factor simplifies field replacement of failed configuration memory.
推薦
Cyclone Series Legacy Configuration
Although Cyclone series FPGAs (EP1C, EP1C3) have internal configuration modes, the EPC2LC22N provides external boot memory for designs requiring the security of off-chip configuration storage. According to Altera's Cyclone configuration handbook, the EPC2LC22N's JTAG programming matches Cyclone's JTAG chain, enabling shared ISP infrastructure. This is useful in defense and aerospace applications where external configuration is preferred.
推薦
Stratix Configuration Memory
For Stratix FPGA designs requiring multi-device configuration chains, the EPC2LC22N serves as one node in a cascaded EPC2 family chain, supporting bitstreams larger than 1.6 Mbit. According to the EPC2 datasheet, the LC core's low power consumption is particularly valuable in Stratix systems where thermal budget is tight. The cascadable design enables Stratix EP1S and EP1SE series boot support with multiple PROMs.
推薦
In-Field FPGA Reconfiguration Systems
The EPC2LC22N's in-system programmability via IEEE 1149.1 JTAG enables in-field FPGA reconfiguration for industrial, military, and aerospace systems where physical PROM replacement is impractical. According to Altera's configuration documentation, JTAG-based ISP supports remote firmware updates via JTAG-over-Ethernet bridges. The PLCC-22 socketed package still allows manual extraction when needed for lab programming.
推薦
推薦產品摘要
工程參考資料，適用於 EPC2LC22N — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPC2LC21N | EPC2LC20N | EPC2L20N |
|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera |
| Package | PLCC-22 | PLCC-22 | PLCC-20 | PLCC-20 |
| Memory Size | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit |
| Core Voltage | 2.5 V (LC) | 2.5 V (LC) | 2.5 V (LC) | 3.3 V (L) |
| JTAG ISP | Yes | Yes | Yes | Yes |
| Cascadable | Yes | Yes | Yes | Yes |
| Speed Grade | Standard | Faster | Standard | Standard |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
主要差異化特點
- Lower 2.5V core supply vs 3.3V L variants (對比EPC2L20N)
- Larger PLCC-22 package for thermal dissipation (對比EPC2LC20N)
- Same PLCC-22 footprint as EPC2LC21N (對比EPC2LC21N)
設計說明
The EPC2LC22N's LC core operates at 2.5V, drawing approximately 50 mA active and 100 uA standby according to the EPC2 datasheet. Ensure the 2.5V rail is decoupled with at least 0.1 uF ceramic plus 10 uF bulk capacitance within 1 inch of the VCC pins. Estimated: total standby power is 0.25 mW, which is negligible but indicates the LC variant's advantage over the 3.3V L variant for low-power designs.
Place the EPC2LC22N within 2 inches of the target FPGA to minimize configuration clock (DCLK) trace length and avoid signal integrity issues. Route JTAG signals (TCK, TMS, TDI, TDO) in a single JTAG chain with the FPGA, using 4.7k pull-ups on TCK/TMS/TDI as recommended by the IEEE 1149.1 specification. The PLCC-22 socket footprint should include provisions for manual extraction without PCB rework.
Do not confuse the EPC2LC22N (2.5V core) with the EPC2L20N (3.3V core) - both have 'LC' or 'L' suffixes that differ by only one letter but require different supply voltages. Mixing them will damage the PROM. According to the Altera datasheet, the EPC2 family uses LC = 2.5V, L = 3.3V, and PC = 5V designations. Verify the exact suffix before placing orders for legacy stock.
合規資訊
Compliance status not specified in verified web data. Altera EPC2 family was originally released in early 2000s, predating widespread RoHS transition; many legacy parts are non-RoHS. Verify with distributor before placing orders for RoHS-restricted markets.
