EPC2LS20U - 1.6Mb FPGA Config PROM, 20-PLCC | Altera
MPN： EPC2LS20U ✗ 停產EPC2LS20U 概覽
What is a configuration PROM? A configuration PROM is a non-volatile serial memory that stores the FPGA's bitstream and serially loads it into the SRAM-based configuration cells of an FPGA on power-up. Because SRAM FPGAs lose their configuration when power is removed, a configuration PROM is required to bootstrap the device at every power cycle. The PROM-to-FPGA chain forms part of the broader hierarchical taxonomy: non-volatile memory -> PROM/EPROM/EEPROM/Flash -> serial configuration memory -> FPGA boot loader. EPC2 family parts sit alongside EPC1, EPC4, EPC8, and EPC16 within Altera's classic configuration device portfolio.
Key features of the EPC2LS20U include 1.6 Mbit of storage, a serial configuration interface compatible with FPP (Fast Passive Parallel), PS, or AS modes of older Altera FPGAs, programmable done/status timing, and a built-in JTAG boundary-scan chain for board-level testing. The 20-PLCC package provides a low-profile socketable solution that simplifies field upgrades and rework on legacy Altera designs.
Typical applications include configuring Altera Cyclone-I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K/6000, and MAX-7000/3000 device families in industrial controllers, telecommunications line cards, and legacy military/aerospace retrofit boards. The wide 3.3V operating range and ISP capability also make the part suitable for designs that must support remote firmware updates over JTAG.
When designing with the EPC2LS20U, note that it is a legacy/obsolete part on Altera's (now Intel FPGA) end-of-life list. Long-term designs should evaluate newer configuration solutions such as Micron/Numonyx flash dual-boot or the Intel/Altera EPCQ-series and the built-in configuration of Cyclone-10/MAX-10 devices. For a true drop-in replacement on the 20-PLCC footprint, EPC2LI20 (industrial temperature grade variant) is the closest same-footprint part.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the Altera datasheet, helping engineers evaluate second-source options for legacy FPGA designs.
直接替換替代品，適用於 EPC2LS20U — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPC2LS20U （相同外形與佔位） — 差異在於 Package, Memory Type, Mounting Type, Interface, Memory Size.
EPC2LI20
✅ 直接替換聯絡詢價
查看資料表 →EPC2L20U
✅ 直接替換聯絡詢價
查看資料表 →EPC2L20
✅ 直接替換聯絡詢價
查看資料表 →EPC2LS20U 最大額定值與電氣特性
| Product Type | In-System Programmable Configuration PROM |
| Memory Density | 1.6 Mbit |
| Operating Voltage (VCC) | 3.3 V |
| 介面 | Altera serial configuration / JTAG |
| Programming Method | In-System Programmable (ISP) via JTAG |
| 封裝 | 20-PLCC (J-lead, 9x9 mm) |
| Lead-Free / RoHS | Yes (per "U" suffix) |
| Supported FPGA Families | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 |
| Configuration Modes | PS (Passive Serial), AS, FPP |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) |
| Done Pin | Yes (open-drain programmable polarity) |
| nSTATUS Pin | Yes (open-drain error flag) |
| nCONFIG Pin | Yes (reset/reconfiguration input) |
| DCLK Output | Yes (configuration clock to FPGA) |
| Compliance | RoHS (Pb-free per U suffix) |
EPC2LS20U 腳位配置
| 腳位 1 | DATA — Configuration data output to FPGA |
| 腳位 2 | DCLK — Configuration clock output to FPGA |
| 腳位 3 | nCONFIG — Configuration control input (active-low) |
| 腳位 4 | nSTATUS — Configuration status output (active-low, open-drain) |
| 腳位 5 | CONF_DONE — Configuration complete flag (open-drain) |
| 腳位 6 | VCC — +3.3V supply voltage |
| 腳位 7 | GND — Ground reference |
| 腳位 8 | TCK — JTAG test clock input |
| 腳位 9 | TMS — JTAG test mode select input |
| 腳位 10 | TDI — JTAG test data input |
| 腳位 11 | TDO — JTAG test data output |
| 腳位 12 | nCE — Chip enable (active-low) |
| 腳位 13 | OE — Output enable (active-high) |
| 腳位 14 | NC — Not connected |
| 腳位 15 | NC — Not connected |
| 腳位 16 | NC — Not connected |
| 腳位 17 | NC — Not connected |
| 腳位 18 | NC — Not connected |
| 腳位 19 | NC — Not connected |
| 腳位 20 | VCC — +3.3V supply (tied to pin 6) |
典型應用
EPC2LS20U 適用於 6 應用s: Cyclone/Stratix FPGA Boot Configuration, APEX-II/ACEX-1K Legacy Board Repair, FLEX-10K/6000 Industrial Controller, Telecommunications Line Card, MAX-7000S/A CPLD Co-Boot, In-System Firmware Upgrade (JTAG ISP).
Cyclone/Stratix FPGA Boot Configuration
The EPC2LS20U stores the 1.6-Mbit configuration bitstream that boots Altera Cyclone-I/II and Stratix/II SRAM-based FPGAs at every power-up. Its Altera serial configuration interface delivers DATA0/DCLK/nCONFIG/nSTATUS/CONF_DONE handshaking directly to the FPGA, eliminating the need for a separate programmer. With 3.3V operation and JTAG ISP, it is well-suited to industrial controllers, telecom line cards, and legacy retrofit designs where field-replaceable boot storage is essential. Compared with built-in flash in modern MAX-10/Cyclone-10 parts, this standalone PROM approach remains preferable for designs that already have a 20-PLCC footprint.
推薦
APEX-II/ACEX-1K Legacy Board Repair
The EPC2LS20U is widely used as a repair/refresh component on legacy APEX-II (EP2A) and ACEX-1K (EP1K) Altera FPGA designs still in service in industrial, military, and aerospace systems. Its 1.6 Mbit density matches the typical APEX-II EP2A15/EP2A25 and ACEX-1K EP1K100 bitstream size exactly, providing full headroom for IP-core configuration. The 20-PLCC package supports socketed replacement, allowing field service technicians to swap out failed boot memory without reflow rework. Designers should stock this part alongside EPC2LI20 for -40C variants.
推薦
FLEX-10K/6000 Industrial Controller
The EPC2LS20U serves as the configuration memory for FLEX-10K (EPF10K) and FLEX-6000 (EPF6016/6024) FPGAs deployed in long-lifecycle industrial controllers. Many of these controllers ship into 15-25 year production programs where the original EPC2 is the only documented boot memory. With ISP via JTAG, technicians can update the bitstream in-circuit without removing the FPGA, enabling remote firmware patches. The 3.3V core aligns with FLEX-10KA and FLEX-10KE devices that share the same supply rail, simplifying power design.
推薦
Telecommunications Line Card
In legacy telecom line cards built around Altera APEX-20KE and FLEX-10KE FPGAs, the EPC2LS20U provides 1.6 Mbit of non-volatile boot storage for the main switching fabric. The JTAG ISP capability enables remote provisioning and field firmware updates through the equipment's built-in test access port (TAP). With its 20-PLCC form factor and proven reliability, the EPC2LS20U remains a dependable choice for service providers maintaining central-office hardware beyond its original OEM support window.
推薦
MAX-7000S/A CPLD Co-Boot
While modern MAX-3000/7000S/A CPLDs are traditionally self-configuring from internal EEPROM, older MAX-7000S designs paired the CPLD with a separate EPC2LS20U for fast power-on configuration in safety-critical systems. The EPC2LS20U's CONF_DONE flag signals the host controller that the CPLD is ready, enabling deterministic startup sequencing in flight-control and rail-signaling applications. The socketable PLCC package supports field replacement in DO-254/DO-178 compliant systems.
推薦
In-System Firmware Upgrade (JTAG ISP)
The EPC2LS20U's JTAG (IEEE 1149.1) ISP capability allows a host controller or test fixture to re-program the PROM in-circuit via the standard 4-wire JTAG TAP. This eliminates the need to remove the chip for firmware updates, dramatically reducing field-service cost in remote or hard-to-access installations. The Altera ByteBlaster II / USB-Blaster cables can be used directly, and the EPC2LS20U supports both JTAG and Altera-proprietary programming modes. For security-sensitive applications, the OTP fuse can lock out re-programming.
推薦
推薦產品摘要
工程參考資料，適用於 EPC2LS20U — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPC2LI20 | EPC2L20U | EPC2L20 | EPC2LI20N | EPC1LC20 |
|---|---|---|---|---|---|---|
| Package | 20-PLCC | 20-PLCC - same | 20-PLCC - same | 20-PLCC - same | 20-PLCC - same | 20-PLCC - same |
| Brand | Altera | Altera - same | Altera - same | Altera - same | Altera - same | Altera - same |
| Memory Density | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.0 Mbit (-37%) |
| Operating Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | Commercial 0C to +70C | Industrial -40C to +85C | Commercial 0C to +70C | Commercial 0C to +70C | Industrial -40C to +85C | Commercial 0C to +70C |
| RoHS / Pb-Free | Yes (U suffix) | Yes | Yes | No (non-RoHS) | Yes | Yes |
| JTAG ISP | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Obsolete | Active (last time buy) | Obsolete | Obsolete | Active | Obsolete |
| Distributor Stock (qty) | Limited broker stock | Active at DigiKey | Limited broker stock | Limited broker stock | Limited stock | Limited broker stock |
主要差異化特點
- Only commercial-temp 3.3V 1.6Mb variant with Pb-free RoHS lead finish (對比EPC2L20)
- Active alternative available with same 20-PLCC footprint (對比EPC2LI20)
- Higher density (1.6Mb) vs EPC1 family (1Mb) (對比EPC1LC20)
設計說明
Estimated: The EPC2LS20U is an obsolete part as of 2026-09-11 - do NOT specify it for new designs. Use the EPC2LI20 (industrial-temp same-footprint variant) for legacy board repair, or migrate to modern EPCQ16 if the PCB footprint can be redesigned. Verify RoHS status by date code and lot number when sourcing from broker stock; non-"U" variants contain Pb-bearing leads and are not RoHS compliant.
Place a 0.1uF decoupling capacitor as close as possible to pin 6 (VCC) and pin 20 (VCC), with a low-impedance ground return to pin 7 (GND). The JTAG TAP pins (TCK/TMS/TDI/TDO) should be routed with characteristic impedance of 50 ohm and kept under 2 inches when possible. Leave TEST pins 14-19 as NC unless the application note explicitly requires them. Pull-up resistors on nSTATUS and CONF_DONE (typically 4.7k ohm to VCC) are required because these are open-drain outputs.
The DCLK output drives the FPGA configuration clock at speeds up to 50 MHz (per Altera datasheet). Series-terminate DCLK with 33-ohm resistor close to the EPC2LS20U output pin if the trace exceeds 2 inches. The DATA line should be source-terminated similarly. Keep DCLK/DATA traces at least 3W (where W = trace width) away from noisy switching power or clock signals to avoid configuration CRC errors at power-up.
Estimated: At 3.3V supply, the EPC2LS20U typically draws 50 mA peak during programming and 10 mA during configuration read-back. Provide a 3.3V rail with at least 100 mA headroom beyond FPGA and other peripheral needs. If the host board has only a 5V rail, add a low-dropout linear regulator (e.g., 3.3V LDO) capable of delivering 250 mA to support programming inrush current. Do not share the EPC2LS20U VCC with noisy switching converter outputs - noise on VCC can corrupt configuration data transfer.
合規資訊
U suffix designates Pb-free/RoHS compliant lead finish per Altera/Intel ordering information. AEC-Q100 not qualified (Altera configuration PROMs are not automotive-grade). REACH, halogen-free, and conflict-minerals status not explicitly documented in available data - set to unknown per Data Authenticity Rules.
