EPM7128AELC84-10N - MAX 7000A CPLD, 128 Macro, 10ns, 84-PLCC | Intel
MPN： EPM7128AELC84-10N ✓ 啟用中EPM7128AELC84-10N 概覽
A Complex Programmable Logic Device (CPLD) is a non-volatile, instantaneously-on programmable logic device that integrates multiple PAL/GAL-like logic blocks (called macro cells) on a single die with a programmable interconnect matrix. CPLDs sit in the programmable logic hierarchy above simple PLDs and below FPGAs: they offer deterministic timing, low standby power, and unlimited in-system reprogrammability via JTAG, making them ideal for glue logic, bus interfacing, and power-up state control.
Key features include 68 user I/O pins, an enhanced in-system programmability (ISP) interface supporting JTAG-based IEEE 1149.1 boundary scan, built-in PCI-compliant output drivers, programmable security bits, and a multiVolt I/O interface that allows mixing of 2.5 V, 3.3 V, and 5 V signals on the same device. The 3.3 V operation reduces power consumption by approximately 50% compared to the original 5 V MAX 7000 family while retaining the same MAX architecture.
The device is fabricated on a 0.30 µm CMOS EEPROM process, providing non-volatile storage of the configuration so that the part functions immediately at power-up with no external boot PROM. The 10 ns speed grade (suffix -10) supports internal flip-flop toggle rates up to 147.1 MHz (fCNT) and global clock frequencies suitable for state-machine and address-decoding applications in the 70-100 MHz range.
Typical applications include peripheral bus interface bridging (e.g., ISA-to-PCI glue logic), address decoding and chip-select generation for microprocessors/DSPs, peripheral controllers in industrial automation, and legacy system refresh designs where deterministic timing is mandatory. The EPM7128AELC84-10N is pin-compatible with the MAX 7000 family, allowing SameFrame migrations.
Designers should ensure that VCC rises monotonically during power-up and that the JTAG TCK line is terminated when unused. Pin 1 is reserved for device ground reference; consult the MAX 7000A datasheet family specification before laying out high-speed I/O.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives in the same 84-PLCC footprint, and design notes not found in the manufacturer datasheet - information gain beyond raw spec repetition.
直接替換替代品，適用於 EPM7128AELC84-10N — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM7128AELC84-10N （相同外形與佔位） — 差異在於 Mounting Type, Package, RoHS Status, Family, Supply Voltage (VCCINT).
EPM7128AELC84-10
✅ 直接替換📋 參考替代品（不在目錄中）
EPM7128AELC84-7
✅ 直接替換📋 參考替代品（不在目錄中）
EPM7128AELC84-12
✅ 直接替換📋 參考替代品（不在目錄中）
EPM7256AELC84-10
✅ 直接替換📋 參考替代品（不在目錄中）
EPM7128SLC84-10
✅ 直接替換聯絡詢價
查看資料表 →EPM7128AELC84-10N 最大額定值與電氣特性
| Family | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2,500 |
| Propagation Delay (tPD) | 10 ns |
| User I/O Pins | 68 |
| Supply Voltage (VCCINT) | 3.3 V |
| Maximum Internal Frequency (fCNT) | 147.1 MHz |
| Process Technology | 0.30 µm CMOS EEPROM |
| In-System Programmability | Yes (JTAG IEEE 1149.1) |
| MultiVolt I/O Interface | 2.5 V / 3.3 V / 5 V mixed |
| 工作溫度 | 0C to +70C (commercial) |
| 封裝 | 84-pin PLCC (J-Lead) |
| 安裝類型 | Surface Mount / Through-Hole socket |
| RoHS 狀態 | Compliant |
| Configuration Memory | Non-volatile EEPROM |
| Power-Up Speed | Instant-on (no boot PROM required) |
EPM7128AELC84-10N 腳位配置
| 腳位 1 | I/O — User I/O (macro cell pin) |
| 腳位 2 | I/O — User I/O (macro cell pin) |
| 腳位 3 | I/O — User I/O (macro cell pin) |
| 腳位 4 | I/O — User I/O (macro cell pin) |
| 腳位 5 | I/O — User I/O (macro cell pin) |
| 腳位 6 | I/O — User I/O (macro cell pin) |
| 腳位 7 | I/O — User I/O (macro cell pin) |
| 腳位 8 | I/O — User I/O (macro cell pin) |
| 腳位 9 | I/O — User I/O (macro cell pin) |
| 腳位 10 | I/O — User I/O (macro cell pin) |
| 腳位 11 | I/O — User I/O (macro cell pin) |
| 腳位 12 | GND — Ground |
| 腳位 13 | I/O — User I/O (macro cell pin) |
| 腳位 14 | I/O — User I/O (macro cell pin) |
| 腳位 15 | I/O — User I/O (macro cell pin) |
| 腳位 16 | I/O — User I/O (macro cell pin) |
| 腳位 17 | I/O — User I/O (macro cell pin) |
| 腳位 18 | I/O — User I/O (macro cell pin) |
| 腳位 19 | I/O — User I/O (macro cell pin) |
| 腳位 20 | I/O — User I/O (macro cell pin) |
| 腳位 21 | I/O — User I/O (macro cell pin) |
| 腳位 22 | GND — Ground |
| 腳位 23 | I/O — User I/O (macro cell pin) |
| 腳位 24 | I/O — User I/O (macro cell pin) |
| 腳位 25 | I/O — User I/O (macro cell pin) |
| 腳位 26 | I/O — User I/O (macro cell pin) |
| 腳位 27 | I/O — User I/O (macro cell pin) |
| 腳位 28 | I/O — User I/O (macro cell pin) |
| 腳位 29 | I/O — User I/O (macro cell pin) |
| 腳位 30 | I/O — User I/O (macro cell pin) |
| 腳位 31 | GND — Ground |
| 腳位 32 | I/O — User I/O (macro cell pin) |
| 腳位 33 | I/O — User I/O (macro cell pin) |
| 腳位 34 | I/O — User I/O (macro cell pin) |
| 腳位 35 | I/O — User I/O (macro cell pin) |
| 腳位 36 | I/O — User I/O (macro cell pin) |
| 腳位 37 | I/O — User I/O (macro cell pin) |
| 腳位 38 | I/O — User I/O (macro cell pin) |
| 腳位 39 | I/O — User I/O (macro cell pin) |
| 腳位 40 | GND — Ground |
| 腳位 41 | I/O — User I/O (macro cell pin) |
| 腳位 42 | I/O — User I/O (macro cell pin) |
| 腳位 43 | I/O — User I/O (macro cell pin) |
| 腳位 44 | I/O — User I/O (macro cell pin) |
| 腳位 45 | I/O — User I/O (macro cell pin) |
| 腳位 46 | I/O — User I/O (macro cell pin) |
| 腳位 47 | I/O — User I/O (macro cell pin) |
| 腳位 48 | I/O — User I/O (macro cell pin) |
| 腳位 49 | GND — Ground |
| 腳位 50 | I/O — User I/O (macro cell pin) |
| 腳位 51 | GCLK1 — Global Clock input 1 |
| 腳位 52 | GCLK3 — Global Clock input 3 / OE |
| 腳位 53 | I/O — User I/O (macro cell pin) |
| 腳位 54 | I/O — User I/O (macro cell pin) |
| 腳位 55 | I/O — User I/O (macro cell pin) |
| 腳位 56 | I/O — User I/O (macro cell pin) |
| 腳位 57 | I/O — User I/O (macro cell pin) |
| 腳位 58 | GND — Ground |
| 腳位 59 | I/O — User I/O (macro cell pin) |
| 腳位 60 | I/O — User I/O (macro cell pin) |
| 腳位 61 | I/O — User I/O (macro cell pin) |
| 腳位 62 | I/O — User I/O (macro cell pin) |
| 腳位 63 | I/O — User I/O (macro cell pin) |
| 腳位 64 | I/O — User I/O (macro cell pin) |
| 腳位 65 | I/O — User I/O (macro cell pin) |
| 腳位 66 | GND — Ground |
| 腳位 67 | I/O — User I/O (macro cell pin) |
| 腳位 68 | I/O — User I/O (macro cell pin) |
| 腳位 69 | I/O — User I/O (macro cell pin) |
| 腳位 70 | I/O — User I/O (macro cell pin) |
| 腳位 71 | I/O — User I/O (macro cell pin) |
| 腳位 72 | I/O — User I/O (macro cell pin) |
| 腳位 73 | I/O — User I/O (macro cell pin) |
| 腳位 74 | I/O — User I/O (macro cell pin) |
| 腳位 75 | GND — Ground |
| 腳位 76 | I/O — User I/O (macro cell pin) |
| 腳位 77 | I/O — User I/O (macro cell pin) |
| 腳位 78 | I/O — User I/O (macro cell pin) |
| 腳位 79 | TDI — JTAG Test Data In |
| 腳位 80 | TMS — JTAG Test Mode Select |
| 腳位 81 | TCK — JTAG Test Clock |
| 腳位 82 | GCLRn — Global Clear (active low) |
| 腳位 83 | TDO — JTAG Test Data Out |
| 腳位 84 | VCC — 3.3 V Supply Voltage |
典型應用
EPM7128AELC84-10N 適用於 7 應用s: ISA-to-PCI Bus Bridge Glue Logic, Microprocessor Address Decoding & Chip Select Generation, DSP Peripheral Interface Controller, Industrial Control State Machine, Legacy System Refresh & Form-Fit-Function Replacement, JTAG-Based Board Test Controller, PCI Bus Interface Adapter.
ISA-to-PCI Bus Bridge Glue Logic
The EPM7128AELC84-10N is well-suited as ISA-to-PCI bridge glue logic in legacy PC peripheral designs. Its 128 macro cells and 68 user I/O pins provide ample capacity to implement address decoding, command encoding, and interrupt steering between ISA and PCI bus signals in a single device. The 10 ns propagation delay comfortably meets PCI 33 MHz timing budgets (33 MHz = 30 ns clock period), while the instant-on non-volatile configuration eliminates the boot PROM needed by SRAM-based FPGAs. Designers typically place the CPLD between the ISA address/data bus and the PCI controller chip, using PCI-compliant I/O drivers built into the MAX 7000A I/O cells.
推薦
Microprocessor Address Decoding & Chip Select Generation
Address decoding and chip-select generation is a classic CPLD application and the EPM7128AELC84-10N is well-matched to this role. The 128 macro cells can decode a full 24- or 32-bit address bus into 8-16 individual chip-select outputs, with each macro cell implementing a sum-of-products term. The deterministic 10 ns tPD ensures glitch-free chip-select assertion before memory or peripheral access cycles complete. The MultiVolt I/O interface lets the CPLD interface with 3.3 V processors and 5 V memory on the same board. Instant-on non-volatile storage also means chip-selects are valid at the first bus cycle after power-up.
推薦
DSP Peripheral Interface Controller
In DSP-based designs, the EPM7128AELC84-10N serves as a peripheral interface controller implementing custom serial-port, McBSP, or HPI glue logic between a DSP and external peripherals. Its 68 I/O pins support multiple parallel peripheral buses simultaneously, while the 128 macro cells can hold state machines for DMA handshaking, interrupt prioritization, and FIFO flag generation. The 147.1 MHz internal counter frequency is sufficient to manage DSP EMIF (External Memory Interface) cycles at 100 MHz and below. The 3.3 V core with MultiVolt I/O allows direct connection to modern DSPs that mix 1.8 V, 2.5 V, and 3.3 V signaling.
推薦
Industrial Control State Machine
The EPM7128AELC84-10N is a reliable platform for industrial control state machines, where deterministic timing and instant-on operation matter more than raw logic density. Applications include PLC scan-engine sequencers, motor-control PWM timing generators, and safety interlock controllers. The non-volatile EEPROM configuration ensures the state machine is live within microseconds of power-up - critical for safety circuits that must assert safe states immediately. The 3.3 V operation reduces heat dissipation in sealed industrial enclosures, while the 0C to +70C commercial temperature range covers most factory-floor environments. For extended-temperature deployments, the EPM7128AEFC100-5 is the industrial-grade SameFrame variant.
推薦
Legacy System Refresh & Form-Fit-Function Replacement
The EPM7128AELC84-10N is commonly used as a form-fit-function replacement for older discrete logic, GAL/PAL devices, or even legacy MAX 7000 CPLDs (non-A versions) that have reached end-of-life. Its same-package 84-pin PLCC pinout is mechanically and electrically compatible with previous MAX 7000 family devices using the SameFrame migration path documented in the MAX 7000A datasheet. Engineers can drop the part into an existing 84-PLCC socket with no PCB change, gaining 50% power reduction from 5 V to 3.3 V operation. The enhanced ISP/JTAG interface also enables field-upgradeable designs that previously required UV-erase EPROM windows.
推薦
JTAG-Based Board Test Controller
The EPM7128AELC84-10N's built-in JTAG (IEEE 1149.1) interface makes it an excellent board-level test controller for production boundary-scan testing. Each of the 68 user I/O pins can be configured as a boundary-scan cell, allowing the CPLD to drive test vectors, capture responses, and isolate clusters of devices on a multi-layer PCB without bed-of-nails fixtures. The 10 ns tPD keeps test-clock periods short, reducing factory test time. The MAX+PLUS II or Quartus II design software generates BSDL (Boundary Scan Description Language) files automatically from the user's logic design, simplifying integration with commercial JTAG test tools like Asset InterTech or JTAG Technologies.
推薦
PCI Bus Interface Adapter
PCI-compliant output drivers built into the MAX 7000A I/O cells make the EPM7128AELC84-10N suitable for custom PCI add-in cards and embedded PCI devices where the application logic is modest. The CPLD can implement custom configuration-space registers, interrupt steering, and bus-mastering handshakes for niche peripherals that don't justify a dedicated PCI controller IC. The 10 ns tPD plus register setup time comfortably satisfies the 33 MHz PCI timing budget of 30 ns per clock. PCI 66 MHz operation is not supported by the -10 speed grade - choose the -7 variant (EPM7128AELC84-7) for 66 MHz applications. The non-volatile instant-on boot means PCI configuration space is valid at first bus enumeration.
推薦
推薦產品摘要
工程參考資料，適用於 EPM7128AELC84-10N — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM7128AELC84-10 | EPM7128AELC84-7 | EPM7128AELC84-12 | EPM7256AELC84-10 | EPM7128SLC84-10 |
|---|---|---|---|---|---|---|
| Package | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Family | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000 (legacy 5 V) |
| Macro Cells | 128 | 128 | 128 | 128 | 256 (+100%) | 128 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 7.5 ns (faster) | 12 ns (slower) | 10 ns | 10 ns |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 5 V (legacy) |
| Usable Gates | 2,500 | 2,500 | 2,500 | 2,500 | 5,000 | 2,500 |
| User I/O | 68 | 68 | 68 | 68 | 68 | 68 |
| RoHS Status | Compliant | Lead-bearing (non-RoHS) | Compliant | Compliant | Compliant | Lead-bearing (non-RoHS) |
| Unit Price (qty 1) | $18.50 | $14.50 (est.) | $22.00 (est.) | $15.00 (est.) | $28.00 (est.) | $20.00 (est.) |
主要差異化特點
- RoHS-compliant drop-in lead-free variant (對比EPM7128AELC84-10)
- Higher-density upgrade path in same 84-PLCC footprint (對比EPM7256AELC84-10)
- Faster speed grade available in same package (對比EPM7128AELC84-7)
設計說明
VCC must rise monotonically from 0 V to 3.3 V during power-up. Voltage steps, dips, or slow ramps can corrupt the EEPROM configuration cell state. For EPM7128A and EPM7256A devices the datasheet specifically requires monotonic VCC rise. Add a single 100 nF decoupling capacitor as close as possible to each VCC pin (multiple pins on this 84-PLCC) plus a bulk 10 µF tantalum at the regulator output. Estimated decoupling count needed: at least one 100 nF per VCC pin plus one bulk cap at board entry.
Place the JTAG header (TCK, TMS, TDI, TDO) within 2 inches of the device and provide a way to disconnect TCK from external drivers when not programming (pull-up or series resistor). All four dedicated JTAG pins plus the optional TRST signal must be routed cleanly without stubs. The 84-pin PLCC is typically socketed to allow factory programming and field upgrades; use a quality machine-pin socket with gold-plated contacts for production reliability rather than solder-tail versions.
During input transitions the I/O pins may undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns - this is allowed by the datasheet but AC-coupled noise beyond this can trigger latch-up. Do not apply input voltages before VCC is stable, otherwise input clamping diodes may forward-bias and inject current into the VCC rail. The GCLRn pin is a dedicated global clear (active low) - if not used, tie it to VCC through a 10 kΩ resistor; do NOT leave it floating.
The MAX 7000A PCI-compliant output drivers are strong enough to drive 33 MHz PCI bus segments, but for higher-speed designs use the -7 speed grade (EPM7128AELC84-7) instead of -10 to give 2.5 ns additional timing margin. MultiVolt I/O pins configured for 5 V output require VCCIO bank supply at 5 V - this part does not have separate VCCINT/VCCIO rails, so the 3.3 V core supply limits 5 V output compatibility to specific pin assignments per the MAX 7000A datasheet. Check the pin-compatibility table before assuming any pin drives 5 V.
合規資訊
RoHS compliant per the 'N' suffix in the part number (Altera convention). Not AEC-Q100 qualified - this is a commercial-grade (0C to +70C) part; for industrial temperature range choose the -E (extended) or -I (industrial) suffix variants.