EPM7128SLC84-10 - MAX 7000 CPLD, 128 Macro, 68 I/O, 10ns | Intel
MPN： EPM7128SLC84-10 ✗ 停產EPM7128SLC84-10 概覽
A CPLD (Complex Programmable Logic Device) is a non-volatile, instantaneously-on programmable logic device that bridges the gap between discrete glue logic and FPGAs. Within the broader taxonomy, the EPM7128SLC84-10 belongs to: CPLD -> PLD -> programmable logic -> digital semiconductor -> integrated circuit. It provides deterministic, fixed propagation delay across all 128 macrocells, making it ideal for glue-logic, bus interfacing, address decoding, and state-machine replacement. Unlike SRAM-based FPGAs, the EEPROM configuration cell retains the bitstream without external boot memory and powers up ready to operate.
Key specifications include a maximum operating frequency of 125 MHz, 250 MHz internal frequency, 4.5 ns propagation delay (per the Alldatasheet index), and a maximum of 2500 usable gates. The device supports programmable speed/power optimization, allowing individual macrocells to run at reduced power with a small timing penalty. The 84-pin Plastic Leaded Chip Carrier (PLCC) package uses J-bend surface-mount leads suitable for socketed programming and production assembly.
The MAX 7000S architecture employs a programmable interconnect array (PIA) that routes any macrocell output or I/O pin to any other macrocell input, providing full routability. Each macrocell contains a programmable AND/OR/flip-flop array with configurable clear, preset, clock, and output-enable controls. MultiVolt I/O pins permit interfacing with 2.5 V, 3.3 V, and 5 V logic without external level translation. The on-chip JTAG boundary-scan logic supports IEEE 1149.1 testing and in-system programming.
Typical applications include bus interface bridging (e.g., 8/16/32-bit microprocessor glue logic), peripheral controller state machines, address decoding and chip-select generation, board-level reset sequencing, LED and seven-segment display multiplexing, and legacy industrial-control logic upgrades. Designers choose this part when deterministic timing, instant-on behavior, and single-chip simplicity outweigh the higher logic density of an FPGA.
A primary design consideration is the 5 V VCC requirement; modern 3.3 V-only systems need a separate rail. JTAG chain ordering must keep TCK/TMS/TDO/TDI integrity when multiple devices share the boundary-scan bus. For new designs, verify the Altera/Intel MAX II or MAX V equivalent if lower power or 1.8 V support is required.
This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes drawn from the manufacturer MAX 7000 family datasheet and verified web sources.
直接替換替代品，適用於 EPM7128SLC84-10 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM7128SLC84-10 （相同外形與佔位） — 差異在於 Package, RoHS Status, Mounting Type, Supply Voltage (VCCINT), Operating Temperature.
EPM7128ELC84-10
✅ 直接替換聯絡詢價
查看資料表 →EPM7128ELC84-12
✅ 直接替換聯絡詢價
查看資料表 →EPM7128ELC84-20
✅ 直接替換聯絡詢價
查看資料表 →EPM7128SLC84-15N
✅ 直接替換聯絡詢價
查看資料表 →EPM7128AELC84-10N
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM7128SLC84-10 最大額定值與電氣特性
| Family | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| Logic Gates | 2500 |
| User I/Os | 68 |
| Total Package Pins | 84 |
| 封裝 | PLCC-84 (J-lead) |
| Propagation Delay (tpd) | 10 ns |
| Maximum Operating Frequency | 125 MHz |
| Internal Frequency | 250 MHz |
| Supply Voltage (VCCINT) | 5 V |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5 V |
| Program Memory Type | EEPROM (in-system programmable) |
| JTAG (IEEE 1149.1) | Yes |
| 工作溫度 | 0C to +70C (Commercial) |
| 安裝類型 | Surface Mount (J-bend) |
| RoHS 狀態 | Non-compliant (contains lead in PLCC) |
EPM7128SLC84-10 腳位配置
| 腳位 1 | INPUT/GCLK1 — Global clock input 1 (dedicated) |
| 腳位 2 | I/O — User I/O pin |
| 腳位 3 | I/O — User I/O pin |
| 腳位 4 | I/O — User I/O pin |
| 腳位 5 | I/O — User I/O pin |
| 腳位 6 | I/O — User I/O pin |
| 腳位 7 | I/O — User I/O pin |
| 腳位 8 | I/O — User I/O pin |
| 腳位 9 | I/O — User I/O pin |
| 腳位 10 | GND — Ground |
| 腳位 11 | I/O — User I/O pin |
| 腳位 12 | I/O — User I/O pin |
| 腳位 13 | I/O — User I/O pin |
| 腳位 14 | I/O — User I/O pin |
| 腳位 15 | TDI — JTAG Test Data In (dedicated) |
| 腳位 16 | TMS — JTAG Test Mode Select (dedicated) |
| 腳位 17 | TCK — JTAG Test Clock (dedicated) |
| 腳位 18 | I/O — User I/O pin |
| 腳位 19 | I/O — User I/O pin |
| 腳位 20 | I/O — User I/O pin |
| 腳位 21 | VCC — 5 V supply |
| 腳位 22 | I/O — User I/O pin |
| 腳位 23 | I/O — User I/O pin |
| 腳位 24 | I/O — User I/O pin |
| 腳位 25 | I/O — User I/O pin |
| 腳位 26 | I/O — User I/O pin |
| 腳位 27 | I/O — User I/O pin |
| 腳位 28 | GND — Ground |
| 腳位 29 | I/O — User I/O pin |
| 腳位 30 | I/O — User I/O pin |
| 腳位 31 | I/O — User I/O pin |
| 腳位 32 | I/O — User I/O pin |
| 腳位 33 | I/O — User I/O pin |
| 腳位 34 | OE1 — Output enable 1 (dedicated) |
| 腳位 35 | OE2/GCLK2 — Output enable 2 / Global clock 2 (dedicated) |
| 腳位 36 | I/O — User I/O pin |
| 腳位 37 | I/O — User I/O pin |
| 腳位 38 | I/O — User I/O pin |
| 腳位 39 | I/O — User I/O pin |
| 腳位 40 | I/O — User I/O pin |
| 腳位 41 | GND — Ground |
| 腳位 42 | I/O — User I/O pin |
| 腳位 43 | I/O — User I/O pin |
| 腳位 44 | I/O — User I/O pin |
| 腳位 45 | I/O — User I/O pin |
| 腳位 46 | I/O — User I/O pin |
| 腳位 47 | I/O — User I/O pin |
| 腳位 48 | VCC — 5 V supply |
| 腳位 49 | I/O — User I/O pin |
| 腳位 50 | I/O — User I/O pin |
| 腳位 51 | I/O — User I/O pin |
| 腳位 52 | I/O — User I/O pin |
| 腳位 53 | I/O — User I/O pin |
| 腳位 54 | I/O — User I/O pin |
| 腳位 55 | I/O — User I/O pin |
| 腳位 56 | GND — Ground |
| 腳位 57 | I/O — User I/O pin |
| 腳位 58 | I/O — User I/O pin |
| 腳位 59 | I/O — User I/O pin |
| 腳位 60 | I/O — User I/O pin |
| 腳位 61 | INPUT — Direct input (dedicated, fastest path) |
| 腳位 62 | I/O — User I/O pin |
| 腳位 63 | I/O — User I/O pin |
| 腳位 64 | I/O — User I/O pin |
| 腳位 65 | I/O — User I/O pin |
| 腳位 66 | VCC — 5 V supply |
| 腳位 67 | I/O — User I/O pin |
| 腳位 68 | I/O — User I/O pin |
| 腳位 69 | I/O — User I/O pin |
| 腳位 70 | I/O — User I/O pin |
| 腳位 71 | GND — Ground |
| 腳位 72 | I/O — User I/O pin |
| 腳位 73 | I/O — User I/O pin |
| 腳位 74 | I/O — User I/O pin |
| 腳位 75 | I/O — User I/O pin |
| 腳位 76 | I/O — User I/O pin |
| 腳位 77 | I/O — User I/O pin |
| 腳位 78 | TDO — JTAG Test Data Out (dedicated) |
| 腳位 79 | I/O — User I/O pin |
| 腳位 80 | I/O — User I/O pin |
| 腳位 81 | I/O — User I/O pin |
| 腳位 82 | I/O — User I/O pin |
| 腳位 83 | I/O — User I/O pin |
| 腳位 84 | VCC — 5 V supply |
典型應用
EPM7128SLC84-10 適用於 6 應用s: Microprocessor Bus Glue Logic, Address Decoding and Chip-Select Generation, State Machine Controller (Mealy/Moore), Board-Level Reset and Watchdog Sequencing, LED Display Multiplexing and Scanning, Legacy Industrial Control Logic Replacement.
Microprocessor Bus Glue Logic
The EPM7128SLC84-10's 128 macrocells and 68 user I/Os make it ideal for implementing microprocessor bus glue logic that requires deterministic 10 ns propagation delay. In a typical 8/16/32-bit microcontroller or DSP board, the CPLD decodes chip-selects, generates wait-state timing, and bridges asynchronous peripheral buses. The MultiVolt I/O allows direct interface to both 5 V processor buses and 3.3 V peripheral logic without external level translators. With 2500 usable gates and 125 MHz fmax, the part can replace 4-6 discrete PAL/GAL devices plus their interconnect, reducing board area and BOM cost. The JTAG interface enables in-system reprogramming for late-stage firmware updates. Pair with a 74HC245 or 74LVT245 bus transceiver for bidirectional buffering.
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Address Decoding and Chip-Select Generation
The EPM7128SLC84-10 is well-suited for address decoding and chip-select generation in memory-mapped systems with up to 24 address lines. Its 128 macrocells can decode 16-32 independent address ranges with programmable wait-state insertion and timing skew control. The 10 ns pin-to-pin delay ensures that chip-selects become valid within one clock cycle of address assertion, critical for high-speed memory interfaces. Each macrocell's programmable AND/OR array can implement complex address comparison logic (e.g., burst-mode ROM, page-mode DRAM) without external gates. The EEPROM configuration retains the decode map through power cycles, eliminating the boot-time ambiguity of SRAM-based controllers. Use the device alongside a 27C256 EPROM or 6264 SRAM as the target memory.
推薦
State Machine Controller (Mealy/Moore)
Implementing state machines is a core strength of the EPM7128SLC84-10, with each of the 128 macrocells containing a programmable flip-flop suitable for state-bit storage. The deterministic 10 ns delay across all macrocells means state transitions occur in fixed time, simplifying timing closure in safety-critical industrial controllers. The device can implement 32-64 state Moore or Mealy machines with multiple inputs and outputs, including handshaking protocols (e.g., SPI, I2C master, UART). The programmable output enable (OE) network allows bus arbitration and tri-state control without external logic. In-system JTAG programming enables rapid state-machine iteration during development. Combine with an external crystal oscillator for precise baud-rate generation.
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Board-Level Reset and Watchdog Sequencing
Power-on reset and multi-rail sequencing benefit from the EPM7128SLC84-10's programmable timing and EEPROM memory. The CPLD can generate sequenced reset signals for up to 8 voltage rails with adjustable delay (programmable via JTAG), eliminating the need for cascaded RC delay networks or discrete reset ICs. Its 5 V VCC and 68 I/Os allow direct interface to legacy supervisory circuits and modern PMICs. The deterministic 10 ns delay ensures reset assertions meet processor power-good timing without metastability. Pair with a MAX811 or TPS3823 voltage supervisor for the primary reset input to the CPLD.
推薦
LED Display Multiplexing and Scanning
The EPM7128SLC84-10's 68 user I/Os and 125 MHz internal frequency make it an effective LED display multiplexing controller for 7-segment, dot-matrix, or bar-graph displays with up to 64 segments. Each macrocell can drive a segment line through a current-limiting resistor, while the global clock network synchronizes multiplexing at the user-defined refresh rate (typically 100-1000 Hz). The EEPROM configuration stores character maps and animation sequences without external ROM. The deterministic timing eliminates flicker artifacts that plague microcontroller-based drivers with interrupt jitter. The PLCC-84 package's J-leads simplify prototype socket replacement during development. Combine with ULN2003A or TPIC6B595 high-side drivers for high-current LED arrays.
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Legacy Industrial Control Logic Replacement
Modernizing obsolete 74LS/74F-series discrete logic boards is a classic application for the EPM7128SLC84-10, where it can replace 6-10 standard logic ICs (counters, decoders, multiplexers, latches) in a single PLCC-84 package. The 128 macrocells and 2500-gate capacity are sufficient to consolidate entire timing/control sections of PLCs, motor controllers, and instrumentation front-ends. The in-system JTAG programmability allows last-minute logic changes without board respins, reducing time-to-market for industrial OEMs. The commercial 0C to +70C temperature range suits most factory-floor enclosures. The 5 V VCC matches legacy supply rails without level translation. Note that this part is obsolete; for new industrial designs, select the MAX V 5M240Z with industrial -40C to +85C support.
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推薦產品摘要
工程參考資料，適用於 EPM7128SLC84-10 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM7128ELC84-10 | EPM7128ELC84-12 | EPM7128ELC84-20 | EPM7128SLC84-15N | EPM7128AELC84-10N |
|---|---|---|---|---|---|---|
| Package | PLCC-84 | PLCC-84 - same | PLCC-84 - same | PLCC-84 - same | PLCC-84 - same | PLCC-84 - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Family | MAX 7000S | MAX 7000E | MAX 7000E | MAX 7000E | MAX 7000S | MAX 7000AE |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tpd) | 10 ns | 10 ns | 12 ns | 20 ns | 15 ns | 10 ns |
| User I/Os | 68 | 68 | 68 | 68 | 68 | 68 |
| VCCINT | 5 V | 5 V | 5 V | 5 V | 5 V | 3.3 V |
| Output Enables | 2 | 6 | 6 | 6 | 2 | 6 |
| Lifecycle | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Drop-in Compatible | N/A (this part) | Yes - same package, identical pinout | Yes - same package, identical pinout | Yes - same package, identical pinout | Yes - same package, identical pinout | Pin-compatible but 3.3 V supply |
主要差異化特點
- MAX 7000S variant with simpler architecture than MAX 7000E (對比EPM7128ELC84-10)
- 10 ns tpd is the fastest grade in the MAX 7128 family (對比EPM7128SLC84-15N)
- 5 V VCCINT matches legacy industrial systems (對比EPM7128AELC84-10N)
設計說明
The EPM7128SLC84-10 requires a stable 5 V VCCINT supply with maximum tolerance of +/-5%. Bulk decoupling of 10-100 uF tantalum plus 0.1 uF ceramic at each VCC pin (the PLCC-84 has 4 VCC pins: 21, 48, 66, 84) is mandatory. ICC active current can reach 200-300 mA during JTAG programming - ensure the regulator has adequate headroom. MultiVolt I/O banks (VCCIO) can be powered from 2.5 V, 3.3 V, or 5 V independently, but all I/Os in a given bank share the same VCCIO rail.
Use a PLCC-84 socket (e.g., 3M 8484 or equivalent) during prototyping to allow device swapping and factory programming. For production assembly, the J-leads accept standard surface-mount soldering profiles (peak 235C for SnPb, 245C for lead-free). Maintain a 0.635 mm (25 mil) clearance between PLCC pads and any via or trace. Ground plane should be a continuous pour under the device to reduce VCC inductance. JTAG chain ordering must keep TCK/TMS shared across all devices with TDI/TDO daisy-chained - verify chain integrity with the Altera/Intel ByteBlaster software before board bring-up.
Three pitfalls recur in EPM7128SLC84-10 designs: (1) Do not leave JTAG pins floating - tie TMS and TDI high through 10 kohm pull-ups to VCCIO. (2) Do not exceed 5.25 V on VCCINT or any I/O pin - the MultiVolt feature is forward-compatible only (5 V tolerant when VCCIO is 3.3 V) and the absolute maximum ratings are strict. (3) Do not program the device without verifying the JTAG IDCODE - mismatched chain order causes programming to fail or, worse, to overwrite a different device. Use the Altera/Intel Quartus programmer to scan the chain first.
合規資訊
PLCC-84 package uses SnPb J-lead finish - non-RoHS. The N-suffix variants (e.g., EPM7128SLC84-10N) use lead-free matte-tin plating and are RoHS compliant. REACH compliant per Intel product declaration. Not AEC-Q100 qualified - this is a commercial-grade CPLD.
