EPM7128AELC84-10N - MAX 7000A CPLD, 128 Macro, 10ns, 84-PLCC | Intel
MPN: EPM7128AELC84-10N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.9 | $5,950.00 |
| 1,000 | $10.45 | $10,450.00 |
Drop-in alternatives for EPM7128AELC84-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128AELC84-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7128AELC84-7
β Drop-Inπ Reference alternative (not in catalog)
EPM7128AELC84-12
β Drop-Inπ Reference alternative (not in catalog)
EPM7256AELC84-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SLC84-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7128AELC84-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2,500 |
| Propagation Delay (tPD) | 10 ns |
| User I/O Pins | 68 |
| Supply Voltage (VCCINT) | 3.3 V |
| Maximum Internal Frequency (fCNT) | 147.1 MHz |
| Process Technology | 0.30 Β΅m CMOS EEPROM |
| In-System Programmability | Yes (JTAG IEEE 1149.1) |
| MultiVolt I/O Interface | 2.5 V / 3.3 V / 5 V mixed |
| Operating Temperature | 0C to +70C (commercial) |
| Package | 84-pin PLCC (J-Lead) |
| Mounting Type | Surface Mount / Through-Hole socket |
| RoHS Status | Compliant |
| Configuration Memory | Non-volatile EEPROM |
| Power-Up Speed | Instant-on (no boot PROM required) |
EPM7128AELC84-10N Pin Configuration
| Pin 1 | I/O β User I/O (macro cell pin) |
| Pin 2 | I/O β User I/O (macro cell pin) |
| Pin 3 | I/O β User I/O (macro cell pin) |
| Pin 4 | I/O β User I/O (macro cell pin) |
| Pin 5 | I/O β User I/O (macro cell pin) |
| Pin 6 | I/O β User I/O (macro cell pin) |
| Pin 7 | I/O β User I/O (macro cell pin) |
| Pin 8 | I/O β User I/O (macro cell pin) |
| Pin 9 | I/O β User I/O (macro cell pin) |
| Pin 10 | I/O β User I/O (macro cell pin) |
| Pin 11 | I/O β User I/O (macro cell pin) |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O (macro cell pin) |
| Pin 14 | I/O β User I/O (macro cell pin) |
| Pin 15 | I/O β User I/O (macro cell pin) |
| Pin 16 | I/O β User I/O (macro cell pin) |
| Pin 17 | I/O β User I/O (macro cell pin) |
| Pin 18 | I/O β User I/O (macro cell pin) |
| Pin 19 | I/O β User I/O (macro cell pin) |
| Pin 20 | I/O β User I/O (macro cell pin) |
| Pin 21 | I/O β User I/O (macro cell pin) |
| Pin 22 | GND β Ground |
| Pin 23 | I/O β User I/O (macro cell pin) |
| Pin 24 | I/O β User I/O (macro cell pin) |
| Pin 25 | I/O β User I/O (macro cell pin) |
| Pin 26 | I/O β User I/O (macro cell pin) |
| Pin 27 | I/O β User I/O (macro cell pin) |
| Pin 28 | I/O β User I/O (macro cell pin) |
| Pin 29 | I/O β User I/O (macro cell pin) |
| Pin 30 | I/O β User I/O (macro cell pin) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O (macro cell pin) |
| Pin 33 | I/O β User I/O (macro cell pin) |
| Pin 34 | I/O β User I/O (macro cell pin) |
| Pin 35 | I/O β User I/O (macro cell pin) |
| Pin 36 | I/O β User I/O (macro cell pin) |
| Pin 37 | I/O β User I/O (macro cell pin) |
| Pin 38 | I/O β User I/O (macro cell pin) |
| Pin 39 | I/O β User I/O (macro cell pin) |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β User I/O (macro cell pin) |
| Pin 42 | I/O β User I/O (macro cell pin) |
| Pin 43 | I/O β User I/O (macro cell pin) |
| Pin 44 | I/O β User I/O (macro cell pin) |
| Pin 45 | I/O β User I/O (macro cell pin) |
| Pin 46 | I/O β User I/O (macro cell pin) |
| Pin 47 | I/O β User I/O (macro cell pin) |
| Pin 48 | I/O β User I/O (macro cell pin) |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O (macro cell pin) |
| Pin 51 | GCLK1 β Global Clock input 1 |
| Pin 52 | GCLK3 β Global Clock input 3 / OE |
| Pin 53 | I/O β User I/O (macro cell pin) |
| Pin 54 | I/O β User I/O (macro cell pin) |
| Pin 55 | I/O β User I/O (macro cell pin) |
| Pin 56 | I/O β User I/O (macro cell pin) |
| Pin 57 | I/O β User I/O (macro cell pin) |
| Pin 58 | GND β Ground |
| Pin 59 | I/O β User I/O (macro cell pin) |
| Pin 60 | I/O β User I/O (macro cell pin) |
| Pin 61 | I/O β User I/O (macro cell pin) |
| Pin 62 | I/O β User I/O (macro cell pin) |
| Pin 63 | I/O β User I/O (macro cell pin) |
| Pin 64 | I/O β User I/O (macro cell pin) |
| Pin 65 | I/O β User I/O (macro cell pin) |
| Pin 66 | GND β Ground |
| Pin 67 | I/O β User I/O (macro cell pin) |
| Pin 68 | I/O β User I/O (macro cell pin) |
| Pin 69 | I/O β User I/O (macro cell pin) |
| Pin 70 | I/O β User I/O (macro cell pin) |
| Pin 71 | I/O β User I/O (macro cell pin) |
| Pin 72 | I/O β User I/O (macro cell pin) |
| Pin 73 | I/O β User I/O (macro cell pin) |
| Pin 74 | I/O β User I/O (macro cell pin) |
| Pin 75 | GND β Ground |
| Pin 76 | I/O β User I/O (macro cell pin) |
| Pin 77 | I/O β User I/O (macro cell pin) |
| Pin 78 | I/O β User I/O (macro cell pin) |
| Pin 79 | TDI β JTAG Test Data In |
| Pin 80 | TMS β JTAG Test Mode Select |
| Pin 81 | TCK β JTAG Test Clock |
| Pin 82 | GCLRn β Global Clear (active low) |
| Pin 83 | TDO β JTAG Test Data Out |
| Pin 84 | VCC β 3.3 V Supply Voltage |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128AELC84-10N is suitable for 7 applications: ISA-to-PCI Bus Bridge Glue Logic, Microprocessor Address Decoding & Chip Select Generation, DSP Peripheral Interface Controller, Industrial Control State Machine, Legacy System Refresh & Form-Fit-Function Replacement, JTAG-Based Board Test Controller, PCI Bus Interface Adapter.
ISA-to-PCI Bus Bridge Glue Logic
The EPM7128AELC84-10N is well-suited as ISA-to-PCI bridge glue logic in legacy PC peripheral designs. Its 128 macro cells and 68 user I/O pins provide ample capacity to implement address decoding, command encoding, and interrupt steering between ISA and PCI bus signals in a single device. The 10 ns propagation delay comfortably meets PCI 33 MHz timing budgets (33 MHz = 30 ns clock period), while the instant-on non-volatile configuration eliminates the boot PROM needed by SRAM-based FPGAs. Designers typically place the CPLD between the ISA address/data bus and the PCI controller chip, using PCI-compliant I/O drivers built into the MAX 7000A I/O cells.
Recommended
Microprocessor Address Decoding & Chip Select Generation
Address decoding and chip-select generation is a classic CPLD application and the EPM7128AELC84-10N is well-matched to this role. The 128 macro cells can decode a full 24- or 32-bit address bus into 8-16 individual chip-select outputs, with each macro cell implementing a sum-of-products term. The deterministic 10 ns tPD ensures glitch-free chip-select assertion before memory or peripheral access cycles complete. The MultiVolt I/O interface lets the CPLD interface with 3.3 V processors and 5 V memory on the same board. Instant-on non-volatile storage also means chip-selects are valid at the first bus cycle after power-up.
Recommended
DSP Peripheral Interface Controller
In DSP-based designs, the EPM7128AELC84-10N serves as a peripheral interface controller implementing custom serial-port, McBSP, or HPI glue logic between a DSP and external peripherals. Its 68 I/O pins support multiple parallel peripheral buses simultaneously, while the 128 macro cells can hold state machines for DMA handshaking, interrupt prioritization, and FIFO flag generation. The 147.1 MHz internal counter frequency is sufficient to manage DSP EMIF (External Memory Interface) cycles at 100 MHz and below. The 3.3 V core with MultiVolt I/O allows direct connection to modern DSPs that mix 1.8 V, 2.5 V, and 3.3 V signaling.
Recommended
Industrial Control State Machine
The EPM7128AELC84-10N is a reliable platform for industrial control state machines, where deterministic timing and instant-on operation matter more than raw logic density. Applications include PLC scan-engine sequencers, motor-control PWM timing generators, and safety interlock controllers. The non-volatile EEPROM configuration ensures the state machine is live within microseconds of power-up - critical for safety circuits that must assert safe states immediately. The 3.3 V operation reduces heat dissipation in sealed industrial enclosures, while the 0C to +70C commercial temperature range covers most factory-floor environments. For extended-temperature deployments, the EPM7128AEFC100-5 is the industrial-grade SameFrame variant.
Recommended
Legacy System Refresh & Form-Fit-Function Replacement
The EPM7128AELC84-10N is commonly used as a form-fit-function replacement for older discrete logic, GAL/PAL devices, or even legacy MAX 7000 CPLDs (non-A versions) that have reached end-of-life. Its same-package 84-pin PLCC pinout is mechanically and electrically compatible with previous MAX 7000 family devices using the SameFrame migration path documented in the MAX 7000A datasheet. Engineers can drop the part into an existing 84-PLCC socket with no PCB change, gaining 50% power reduction from 5 V to 3.3 V operation. The enhanced ISP/JTAG interface also enables field-upgradeable designs that previously required UV-erase EPROM windows.
Recommended
JTAG-Based Board Test Controller
The EPM7128AELC84-10N's built-in JTAG (IEEE 1149.1) interface makes it an excellent board-level test controller for production boundary-scan testing. Each of the 68 user I/O pins can be configured as a boundary-scan cell, allowing the CPLD to drive test vectors, capture responses, and isolate clusters of devices on a multi-layer PCB without bed-of-nails fixtures. The 10 ns tPD keeps test-clock periods short, reducing factory test time. The MAX+PLUS II or Quartus II design software generates BSDL (Boundary Scan Description Language) files automatically from the user's logic design, simplifying integration with commercial JTAG test tools like Asset InterTech or JTAG Technologies.
Recommended
PCI Bus Interface Adapter
PCI-compliant output drivers built into the MAX 7000A I/O cells make the EPM7128AELC84-10N suitable for custom PCI add-in cards and embedded PCI devices where the application logic is modest. The CPLD can implement custom configuration-space registers, interrupt steering, and bus-mastering handshakes for niche peripherals that don't justify a dedicated PCI controller IC. The 10 ns tPD plus register setup time comfortably satisfies the 33 MHz PCI timing budget of 30 ns per clock. PCI 66 MHz operation is not supported by the -10 speed grade - choose the -7 variant (EPM7128AELC84-7) for 66 MHz applications. The non-volatile instant-on boot means PCI configuration space is valid at first bus enumeration.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128AELC84-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AELC84-10 | EPM7128AELC84-7 | EPM7128AELC84-12 | EPM7256AELC84-10 | EPM7128SLC84-10 |
|---|---|---|---|---|---|---|
| Package | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Family | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000 (legacy 5 V) |
| Macro Cells | 128 | 128 | 128 | 128 | 256 (+100%) | 128 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 7.5 ns (faster) | 12 ns (slower) | 10 ns | 10 ns |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 5 V (legacy) |
| Usable Gates | 2,500 | 2,500 | 2,500 | 2,500 | 5,000 | 2,500 |
| User I/O | 68 | 68 | 68 | 68 | 68 | 68 |
| RoHS Status | Compliant | Lead-bearing (non-RoHS) | Compliant | Compliant | Compliant | Lead-bearing (non-RoHS) |
| Unit Price (qty 1) | $18.50 | $14.50 (est.) | $22.00 (est.) | $15.00 (est.) | $28.00 (est.) | $20.00 (est.) |
Key Differentiators
- RoHS-compliant drop-in lead-free variant (vs EPM7128AELC84-10)
- Higher-density upgrade path in same 84-PLCC footprint (vs EPM7256AELC84-10)
- Faster speed grade available in same package (vs EPM7128AELC84-7)
Design Notes
VCC must rise monotonically from 0 V to 3.3 V during power-up. Voltage steps, dips, or slow ramps can corrupt the EEPROM configuration cell state. For EPM7128A and EPM7256A devices the datasheet specifically requires monotonic VCC rise. Add a single 100 nF decoupling capacitor as close as possible to each VCC pin (multiple pins on this 84-PLCC) plus a bulk 10 Β΅F tantalum at the regulator output. Estimated decoupling count needed: at least one 100 nF per VCC pin plus one bulk cap at board entry.
Place the JTAG header (TCK, TMS, TDI, TDO) within 2 inches of the device and provide a way to disconnect TCK from external drivers when not programming (pull-up or series resistor). All four dedicated JTAG pins plus the optional TRST signal must be routed cleanly without stubs. The 84-pin PLCC is typically socketed to allow factory programming and field upgrades; use a quality machine-pin socket with gold-plated contacts for production reliability rather than solder-tail versions.
During input transitions the I/O pins may undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns - this is allowed by the datasheet but AC-coupled noise beyond this can trigger latch-up. Do not apply input voltages before VCC is stable, otherwise input clamping diodes may forward-bias and inject current into the VCC rail. The GCLRn pin is a dedicated global clear (active low) - if not used, tie it to VCC through a 10 kΞ© resistor; do NOT leave it floating.
The MAX 7000A PCI-compliant output drivers are strong enough to drive 33 MHz PCI bus segments, but for higher-speed designs use the -7 speed grade (EPM7128AELC84-7) instead of -10 to give 2.5 ns additional timing margin. MultiVolt I/O pins configured for 5 V output require VCCIO bank supply at 5 V - this part does not have separate VCCINT/VCCIO rails, so the 3.3 V core supply limits 5 V output compatibility to specific pin assignments per the MAX 7000A datasheet. Check the pin-compatibility table before assuming any pin drives 5 V.
Compliance Information
RoHS compliant per the 'N' suffix in the part number (Altera convention). Not AEC-Q100 qualified - this is a commercial-grade (0C to +70C) part; for industrial temperature range choose the -E (extended) or -I (industrial) suffix variants.
