EPM7128ELC84-10 - 128-Macrocell CPLD, 10ns, 5V, 84-PLCC | Intel
MPN： EPM7128ELC84-10 ✓ 啟用中EPM7128ELC84-10 概覽
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between discrete glue logic and FPGAs in the digital design hierarchy: it provides deterministic, single-clock-cycle propagation delays, instant-on behavior from on-chip EEPROM, and abundant wide-decoding capability, while being simpler and lower-cost than an FPGA. CPLDs are widely used as the "glue logic" tier of a digital system, bridging processors, memories, and peripherals. The MAX 7000 family is a classic EE CPLD architecture organized as Logic Array Blocks (LABs) with a programmable interconnect array (PIA).
Key features of the EPM7128ELC84-10 include 128 macrocells (equivalent to roughly 2500 usable gates), 68 user I/O pins, 12 dedicated input pins, 5V core and I/O operation (the "E" suffix indicates the enhanced 5V family), and 10ns combinatorial propagation delay through the PIA. Per-pin I/O standards include TTL and CMOS, and the device supports in-system programmability (ISP) via the IEEE 1149.1 JTAG interface, plus a 3.3V or 5V programming voltage selection on dedicated pins.
Technically, the MAX 7000 architecture provides predictable timing and high pin-to-pin performance, making it ideal for address decoding, bus interfacing, state-machine control, and asynchronous logic consolidation. Its non-volatile EEPROM cells eliminate the boot PROM required by SRAM FPGAs and remove the need to reload configuration at power-up, a feature that materially simplifies board design.
Typical applications include system-level address decoding for memory and peripherals in 8/16/32-bit microcontroller and microprocessor designs, bus-interface bridging (e.g., 8-bit to 16-bit width translation), state-machine-based I/O control, and legacy industrial glue-logic replacement. The wide 5V tolerance makes it particularly suited to retrofits of legacy 5V systems.
When designing with this part, note that 5V-tolerant I/Os are increasingly rare in newer CPLD/FPGA families; confirm that downstream devices accept 5V inputs before mixing. Also note the 84-pin PLCC is a through-hole-style J-lead socket-compatible package - verify that your board design accommodates a socket or PLCC footprint. The "10" suffix denotes the commercial speed grade (10ns tPD); a "-15" or "-7" grade variant exists if different timing is required.
This page synthesizes distributor stock and pricing, drop-in same-package alternatives, and practical design notes not found in the bare datasheet, helping engineers make a confident, source-cited sourcing decision.
直接替換替代品，適用於 EPM7128ELC84-10 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM7128ELC84-10 （相同外形與佔位） — 差異在於 Mounting Type, Package, RoHS Status, Maximum Operating Frequency, Family.
EPM7128ELC84-15
✅ 直接替換📋 參考替代品（不在目錄中）
EPM7128ELC84-12
✅ 直接替換聯絡詢價
查看資料表 →EPM7128SLC84-10
✅ 直接替換聯絡詢價
查看資料表 →EPM7128AELC84-10N
✅ 直接替換聯絡詢價
查看資料表 →EPM7128ELC84-20
✅ 直接替換聯絡詢價
查看資料表 →EPM7128SLC84-15N
✅ 直接替換聯絡詢價
查看資料表 →EPM7128ELC84-10 最大額定值與電氣特性
| Family | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| User I/Os | 68 |
| Dedicated Inputs | 12 |
| Operating Voltage (VCCINT/VCClO) | 5 V |
| Pin-to-Pin Delay (tPD) | 10 ns |
| 封裝 | 84-pin PLCC (J-Lead) |
| 安裝類型 | Surface Mount / Socket |
| 工作溫度 | 0C to +70C (Commercial) |
| Technology | EEPROM-based CMOS |
| Programming Interface | IEEE 1149.1 (JTAG) ISP |
| In-System Programmable | Yes |
EPM7128ELC84-10 腳位配置
| 腳位 1 | I/O — User I/O (bank 1) |
| 腳位 2 | I/O — User I/O (bank 1) |
| 腳位 3 | I/O — User I/O (bank 1) |
| 腳位 4 | I/O — User I/O (bank 1) |
| 腳位 5 | I/O — User I/O (bank 1) |
| 腳位 6 | I/O — User I/O (bank 1) |
| 腳位 7 | I/O — User I/O (bank 1) |
| 腳位 8 | I/O — User I/O (bank 1) |
| 腳位 9 | I/O — User I/O (bank 1) |
| 腳位 10 | I/O — User I/O (bank 1) |
| 腳位 11 | I/O — User I/O (bank 1) |
| 腳位 12 | GND — Ground |
| 腳位 13 | I/O — User I/O (bank 2) |
| 腳位 14 | I/O — User I/O (bank 2) |
| 腳位 15 | I/O — User I/O (bank 2) |
| 腳位 16 | I/O — User I/O (bank 2) |
| 腳位 17 | I/O — User I/O (bank 2) |
| 腳位 18 | I/O — User I/O (bank 2) |
| 腳位 19 | I/O — User I/O (bank 2) |
| 腳位 20 | I/O — User I/O (bank 2) |
| 腳位 21 | I/O — User I/O (bank 2) |
| 腳位 22 | I/O — User I/O (bank 2) |
| 腳位 23 | I/O — User I/O (bank 2) |
| 腳位 24 | GND — Ground |
| 腳位 25 | TDI — JTAG Test Data In |
| 腳位 26 | TMS — JTAG Test Mode Select |
| 腳位 27 | TCK — JTAG Test Clock |
| 腳位 28 | I/O — User I/O (bank 2) |
| 腳位 29 | I/O — User I/O (bank 2) |
| 腳位 30 | I/O — User I/O (bank 2) |
| 腳位 31 | I/O — User I/O (bank 3) |
| 腳位 32 | I/O — User I/O (bank 3) |
| 腳位 33 | I/O — User I/O (bank 3) |
| 腳位 34 | I/O — User I/O (bank 3) |
| 腳位 35 | I/O — User I/O (bank 3) |
| 腳位 36 | I/O — User I/O (bank 3) |
| 腳位 37 | VCC — 5V supply |
| 腳位 38 | I/O — User I/O (bank 3) |
| 腳位 39 | I/O — User I/O (bank 3) |
| 腳位 40 | I/O — User I/O (bank 3) |
| 腳位 41 | I/O — User I/O (bank 3) |
| 腳位 42 | INPUT/GCLK — Dedicated input / global clock |
| 腳位 43 | INPUT/OE1 — Dedicated input / Output Enable 1 |
| 腳位 44 | INPUT/OE2/GCLK2 — Dedicated input / Output Enable 2 / global clock 2 |
| 腳位 45 | INPUT/CLR — Dedicated input / Clear |
| 腳位 46 | I/O — User I/O (bank 4) |
| 腳位 47 | I/O — User I/O (bank 4) |
| 腳位 48 | I/O — User I/O (bank 4) |
| 腳位 49 | GND — Ground |
| 腳位 50 | I/O — User I/O (bank 4) |
| 腳位 51 | I/O — User I/O (bank 4) |
| 腳位 52 | I/O — User I/O (bank 4) |
| 腳位 53 | I/O — User I/O (bank 4) |
| 腳位 54 | I/O — User I/O (bank 4) |
| 腳位 55 | I/O — User I/O (bank 4) |
| 腳位 56 | I/O — User I/O (bank 4) |
| 腳位 57 | I/O — User I/O (bank 4) |
| 腳位 58 | I/O — User I/O (bank 4) |
| 腳位 59 | I/O — User I/O (bank 4) |
| 腳位 60 | GND — Ground |
| 腳位 61 | I/O — User I/O (bank 4) |
| 腳位 62 | I/O — User I/O (bank 4) |
| 腳位 63 | I/O — User I/O (bank 1) |
| 腳位 64 | I/O — User I/O (bank 1) |
| 腳位 65 | I/O — User I/O (bank 1) |
| 腳位 66 | I/O — User I/O (bank 1) |
| 腳位 67 | I/O — User I/O (bank 1) |
| 腳位 68 | VCC — 5V supply |
| 腳位 69 | I/O — User I/O (bank 1) |
| 腳位 70 | I/O — User I/O (bank 1) |
| 腳位 71 | I/O — User I/O (bank 1) |
| 腳位 72 | I/O — User I/O (bank 1) |
| 腳位 73 | I/O — User I/O (bank 1) |
| 腳位 74 | I/O — User I/O (bank 1) |
| 腳位 75 | TDO — JTAG Test Data Out |
| 腳位 76 | GND — Ground |
| 腳位 77 | INPUT — Dedicated input (bank 1) |
| 腳位 78 | INPUT — Dedicated input (bank 1) |
| 腳位 79 | INPUT — Dedicated input (bank 1) |
| 腳位 80 | INPUT — Dedicated input (bank 1) |
| 腳位 81 | INPUT — Dedicated input (bank 1) |
| 腳位 82 | INPUT — Dedicated input (bank 1) |
| 腳位 83 | INPUT — Dedicated input (bank 1) |
| 腳位 84 | INPUT — Dedicated input (bank 1) |
典型應用
EPM7128ELC84-10 適用於 6 應用s: Microprocessor Address Decoding, Bus Interface Bridging, State Machine Control Logic, Legacy Industrial Glue Logic Replacement, Industrial Control I/O Expansion, Communication Protocol Bridging.
Microprocessor Address Decoding
The EPM7128ELC84-10 fits microprocessor address decoding because its 128 macrocells and 68 user I/Os provide ample logic capacity for full 24-bit or 32-bit address map decoding, while its 10ns tPD adds minimal wait-state insertion on most modern 5V microcontrollers and DSPs. Its non-volatile EEPROM means decoding logic is available instantly on power-up with no boot PROM, simplifying board bring-up. Place the part between the processor and the memory/peripheral bus; each macrocell can implement one chip-select or enable line. Compared to discrete 74-series glue logic, the EPM7128ELC84-10 consolidates dozens of packages into one, reducing board area and improving signal integrity by shortening address decode paths.
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Bus Interface Bridging
The EPM7128ELC84-10 is well suited to bus interface bridging between mismatched widths or voltage standards, since its 5V-tolerant I/Os can directly drive 5V peripherals while its macrocell logic can re-time data across an 8-bit-to-16-bit or 16-bit-to-32-bit boundary. The 10ns pin-to-pin delay keeps bridging latency low, allowing glue between two clock domains at moderate bus frequencies (up to roughly 50 MHz). The non-volatile configuration simplifies in-field firmware updates via JTAG without external boot storage. Use it to consolidate handshake logic, parity generation, or wait-state insertion that would otherwise require several discrete packages.
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State Machine Control Logic
Implementing state machines in the EPM7128ELC84-10 leverages the deterministic single-cycle propagation delay of the MAX 7000 PIA architecture, giving engineers predictable state-transition timing without FPGA fabric overhead. With 128 macrocells, the device can host multiple parallel state machines (e.g., a UART controller, an I/O sequencer, and a watchdog timer) in one chip. The 68 user I/Os comfortably accommodate status LEDs, control outputs, and sensor inputs. The 5V I/O compatibility allows direct interface with industrial sensors and 5V actuator drivers without level shifters. JTAG-based in-system programmability enables on-line state-machine tuning during development without re-spinning the board.
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Legacy Industrial Glue Logic Replacement
The EPM7128ELC84-10 is widely used to replace aging 74HC/74LS glue logic in legacy industrial controllers, where a single CPLD can replace 5 to 20 discrete packages, freeing board area and reducing power consumption. Its 5V tolerance matches the legacy supply rail and 5V peripherals, eliminating the level-shifters that would be required with newer 3.3V-only parts. The 84-pin PLCC socket-compatible package allows direct drop-in retrofit of older PLCC sockets that previously held legacy decode PLDs. The non-volatile EEPROM eliminates battery-backed configuration or external PROMs required by older architectures, increasing long-term reliability.
推薦
Industrial Control I/O Expansion
In PLC-style industrial controllers, the EPM7128ELC84-10 serves as the I/O expansion and conditioning stage, providing 68 user I/Os that can be software-defined as inputs, outputs, or bidirectional signals via JTAG programming. The 5V I/O tolerance interfaces directly with 24V-tolerant opto-isolated input modules via external resistor dividers, and 5V logic outputs can drive relays, solenoids, and LED indicators. The 10ns tPD supports real-time control loops up to a few kHz, sufficient for slow-loop process control and discrete I/O scanning. EEPROM-based configuration means field updates can be made via JTAG without removing the part.
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Communication Protocol Bridging
The EPM7128ELC84-10 is frequently deployed as a low-cost protocol-bridging device, converting between legacy parallel buses (e.g., 8-bit ISA, 16-bit memory-mapped I/O) and serial protocols (UART, SPI, I2C) at speeds up to roughly 50 MHz. Its 128 macrocells can implement the full state machine for a UART/SPI bridge plus FIFO buffer management, and 68 I/Os allow simultaneous parallel-bus and serial-peripheral connections. The deterministic 10ns timing ensures glitch-free protocol handshakes. In-system programmability via JTAG allows firmware updates during commissioning or field service. The 5V tolerance simplifies integration with legacy 5V bus systems common in industrial and telecom hardware.
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推薦產品摘要
工程參考資料，適用於 EPM7128ELC84-10 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM7128ELC84-15 | EPM7128ELC84-12 | EPM7128SLC84-10 | EPM7128AELC84-10N | EPM7128ELC84-20 | EPM7128SLC84-15N |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Operating Voltage | 5V (E-suffix) | 5V (E-suffix) | 5V (E-suffix) | 5V (S-suffix) | 3.3V (A-suffix) | 5V (E-suffix) | 5V (S-suffix) |
| Pin-to-Pin Delay (tPD) | 10 ns | 15 ns | 12 ns | 10 ns | 10 ns | 20 ns | 15 ns |
| User I/Os | 68 | 68 | 68 | 68 | 68 | 68 | 68 |
| Family | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 |
| In-System Programmable | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Technology | EEPROM CMOS | EEPROM CMOS | EEPROM CMOS | EEPROM CMOS | EEPROM CMOS | EEPROM CMOS | EEPROM CMOS |
主要差異化特點
- Standard commercial speed grade (-10) balances speed and availability (對比EPM7128ELC84-15)
- E-suffix 5V operation matches legacy 5V system rails (對比EPM7128AELC84-10N)
- Non-volatile EEPROM means instant-on with no boot PROM (對比EPM7128ELC84-15)
設計說明
Do NOT confuse the E-suffix (EPM7128ELC84-10, 5V) with the A-suffix (EPM7128AELC84-10, 3.3V) - they share the same 84-pin PLCC footprint but are not electrically interchangeable. According to the MAX 7000 datasheet family, applying 5V to an A-suffix part will damage the device, and applying 3.3V to an E-suffix part may not meet VIH thresholds reliably. Always verify the supply voltage before substituting.
The 84-pin PLCC package is socket-compatible and can be installed in a PLCC socket for easy field replacement. According to the MAX 7000 datasheet, place decoupling capacitors (0.1uF ceramic) close to each VCC pin (typically pins 37, 68) and each GND pin (12, 24, 49, 60, 76) to minimize switching noise on the internal logic and JTAG interface. A bulk 10uF tantalum or ceramic capacitor on the VCC rail near the part is recommended.
For designs switching high-frequency signals (above 50 MHz), keep critical clock and JTAG traces short and impedance-controlled. According to the MAX 7000 datasheet, the JTAG pins (TCK, TMS, TDI, TDO at pins 27, 26, 25, 75) should be routed with care to avoid noise coupling during in-system programming. Series termination (33-68 ohm) on long output traces can reduce undershoot/ringing when driving capacitive loads.
Estimated: at 5V VCC, the EPM7128ELC84-10 commercial-grade part dissipates approximately 500 mW to 1 W depending on switching activity and toggle rate. The 84-pin PLCC package has a thermal resistance of roughly 35-45 C/W (theta_JA) in still air, giving a junction temperature rise of 18-45 C above ambient - well within the 0C to +70C commercial range. For industrial-temperature applications (-40C to +85C), use an I-suffix part such as EPM7128ELC84-10I if available.
合規資訊
RoHS/REACH compliance status was not present in the verified web data; legacy CPLD parts from the MAX 7000 family vary by date code and specific part suffix - confirm RoHS compliance with the distributor at the time of purchase. AEC-Q100 is not applicable as the part is commercial-grade.