5M80ZT100A5N vs 5M80ZT100I5N 对比
详细并排对比 5M80ZT100A5N 出自 Altera 和 5M80ZT100I5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | 5M80ZT100A5N | 5M80ZT100I5N |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $1.85 | $7.37 |
| Family | MAX V | MAX V CPLD |
| Macro Cells | 64 | — |
| Logic Elements / LABs | 8 Logic Array Blocks (LABs) | — |
| Maximum User I/O | 80 (in TQFP-100 package) | — |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency (fMAX) | 118.3 MHz | — |
| Core Supply Voltage (VCCINT) | 1.8 V | 1.71 V to 1.89 V (1.8 V typical) |
| I/O Bank Supply Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage banks) | — |
| User Flash Memory (UFM) | 8 Kbits (typical for MAX V 64-macrocell device) | — |
| Configuration Memory | Non-volatile, on-chip flash | Internal non-volatile flash (instant-on) |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | — |
| 工作结温 | -40 C to +125 C (automotive/industrial grade) | — |
| 封装 | 100-pin TQFP (T100) | TQFP-100 (100 pins, 0.5 mm pitch) |
| 安装类型 | Surface Mount | Surface Mount |
| MSL 等级 | 3 (per JEDEC J-STD-020) | MSL3 (per JEDEC J-STD-020) |
| RoHS 状态 | Compliant | Compliant |
| Automotive Qualification | AEC-Q100 (A5N suffix) | — |
| Supply Current (typical) | [DATA_NEEDED: Icc typical] | — |
| Global Clock Networks | 4 | — |
| Lead-Free / Halogen-Free | Yes / Yes (per Altera lead-free roadmap) | — |
| Logic Elements (LE) | — | 80 |
| Macrocells (approx.) | — | 160 |
| User I/O Pins | — | 64 |
| Pin-to-Pin Logic Delay (tPD) | — | 7.5 ns |
| I/O Supply Voltage (VCCIO) | — | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Operating Temperature (Industrial) | — | -40 °C to +100 °C |
| UFM (User Flash Memory) | — | Up to 8 Kbits user-accessible |
| JTAG / ISP | — | IEEE 1149.1 boundary-scan + in-system programming |