EP1S25F1020I6 vs EP1S25F1020C6N 对比
详细并排对比 EP1S25F1020I6 出自 Altera 和 EP1S25F1020C6N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1S25F1020I6 | EP1S25F1020C6N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $1,530.00 | $450.00 |
| Family | Stratix | Stratix |
| Series | Stratix I | — |
| Logic Elements (LEs) | 25,660 | — |
| Logic Array Blocks (LABs) | 2,566 | — |
| Embedded Memory (RAM bits) | 1,944,576 bits (≈ 1.85 Mbits) | — |
| Maximum User I/O | 706 | — |
| Maximum Operating Frequency | 450 MHz (per datasheet reference) | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Supply Voltage | 1.5 V | — |
| 封装 | 1020-ball FC-FBGA (33 x 33 mm, 1 mm pitch) | 1020-ball FC-FBGA (33 x 33 mm, 1.0 mm pitch) |
| 安装类型 | Surface Mount (BGA) | Surface Mount |
| 工作温度 | -40 °C to +85 °C (industrial) | 0C to +85C (Commercial) |
| Configuration | Passive serial, fast passive parallel, JTAG, enhanced configuration device | — |
| On-chip PLL | Yes | — |
| DSP Blocks | Yes (Stratix DSP blocks) | — |
| RoHS 状态 | [DATA_NEEDED: rohs compliance per lot] | [DATA_NEEDED: RoHS status] |
| Logic Elements (LE) | — | 25,660 |
| Logic Cells | — | 25,660 |
| Embedded Memory (bits) | — | 1,944,576 |
| User I/O Pins | — | 706 |
| LABs (Logic Array Blocks) | — | 2,566 |
| Core Supply Voltage (VCCINT) | — | 1.5 V |
| Maximum Internal Clock Frequency | — | 450.05 MHz |
| Configuration Method | — | JTAG or EPC configuration device |
| Family Generation | — | Stratix (1st generation) |