EP20K400FC672-3 vs EP20K400FC672-3X 对比

详细并排对比 EP20K400FC672-3 出自 Altera 和 EP20K400FC672-3X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP20K400FC672-3X EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera

EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera

EP20K400FC672-3X ⚠ 最后一次采购

规格对比

参数 EP20K400FC672-3 EP20K400FC672-3X
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $138.00 $152.40
Family APEX 20K —
Device Logic Elements 16,640 cells —
Typical Gate Count 400,000 system gates —
Maximum User I/Os 502 —
Propagation Delay 2.5 ns —
Internal Performance 167 MHz —
Process Technology 0.22 µm CMOS —
Core Supply Voltage 2.5 V 2.5 V
Logic Family CMOS, SRAM-based APEX 20K
封装 672-pin FC-FBGA 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA)
Package Code BGA —
Number of Terminals 672 —
Terminal Form Ball (BGA) —
Speed Grade -3 (commercial fastest) -3X
工作温度 0 °C to 85 °C 0 °C to 85 °C (commercial)
安装类型 Surface Mount Surface Mount (BGA)
Architecture MultiCore (LUT + Embedded System Blocks) MultiCore (LUT + embedded CAM/RAM)
Programming Method SRAM, JTAG (ByteBlaster) —
生命周期状态 Obsolete / Legacy —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Device Sub-family — EP20K400
Technology — CMOS 0.22 µm
Number of Gates — 400,000 (typical)
Logic Cells — 16,640
Macros / Macrocells — 1664
User I/Os — 502
Dedicated I/O Lines — 496
最大时钟频率 — 181.82 MHz
Typical Propagation Delay — 2.07 ns
Programming Interface — JTAG (IEEE 1149.1) / ByteBlaster / MasterBlaster

数据手册与资源

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