EP20K400FC672-3 vs EP20K400FC672-3X Comparison

Detailed side-by-side comparison of EP20K400FC672-3 by Altera and EP20K400FC672-3X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP20K400FC672-3X EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera

EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera

EP20K400FC672-3X ⚠ Last Time Buy

Specification Comparison

Parameter EP20K400FC672-3 EP20K400FC672-3X
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last Time Buy
Family APEX 20K —
Device Logic Elements 16,640 cells —
Typical Gate Count 400,000 system gates —
Maximum User I/Os 502 —
Propagation Delay 2.5 ns —
Internal Performance 167 MHz —
Process Technology 0.22 µm CMOS —
Core Supply Voltage 2.5 V 2.5 V
Logic Family CMOS, SRAM-based APEX 20K
Package 672-pin FC-FBGA 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA)
Package Code BGA —
Number of Terminals 672 —
Terminal Form Ball (BGA) —
Speed Grade -3 (commercial fastest) -3X
Operating Temperature 0 °C to 85 °C 0 °C to 85 °C (commercial)
Mounting Type Surface Mount Surface Mount (BGA)
Architecture MultiCore (LUT + Embedded System Blocks) MultiCore (LUT + embedded CAM/RAM)
Programming Method SRAM, JTAG (ByteBlaster) —
Lifecycle Status Obsolete / Legacy —
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Device Sub-family — EP20K400
Technology — CMOS 0.22 µm
Number of Gates — 400,000 (typical)
Logic Cells — 16,640
Macros / Macrocells — 1664
User I/Os — 502
Dedicated I/O Lines — 496
Maximum Clock Frequency — 181.82 MHz
Typical Propagation Delay — 2.07 ns
Programming Interface — JTAG (IEEE 1149.1) / ByteBlaster / MasterBlaster

Datasheets & Resources

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