EP2A70B724C8N vs EP2A70B724I-8 对比

详细并排对比 EP2A70B724C8N 出自 Altera 和 EP2A70B724I-8 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP2A70B724C8N EP2A70B724C8N - APEX II FPGA, 3M Gates, 724-FCBGA | Altera / Intel

EP2A70B724C8N - APEX II FPGA, 3M Gates, 724-FCBGA | Altera / Intel

EP2A70B724C8N ⚠ 最后一次采购

规格对比

参数 EP2A70B724C8N EP2A70B724I-8
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $240.00 $119.00
Series APEX II (EP2A70) —
Family FPGA (PLD) APEX II
System Gates 3,000,000 (3 M) 3,000,000
Logic Elements / Cells 67,200 67,200 cells
Macrocells 16 —
Product Terms 32 —
Propagation Delay 2.49 ns —
Maximum Internal Clock Frequency 281 MHz —
Maximum Clock Frequency (fMAX) 1694.91 MHz —
Process Technology 0.15 um CMOS, SRAM-based 0.15 µm CMOS
Core Supply Voltage 1.5 V 1.5 V
Architecture PLA-type / LUT-based —
Package Type FCBGA-724 (square) FCBGA (Flip-Chip Ball Grid Array)
Number of Pins / Balls 724 —
Terminal Pitch 1.270 mm —
安装类型 Surface Mount (BGA) Surface Mount
Maximum User I/O 536 —
Maximum Internal Frequency — 281 MHz
I/O Supply Voltage — 3.3 V
引脚数 — 724
工作温度 — -40 °C to +100 °C (Industrial)
Peak Reflow Temperature — 220 °C (per JEDEC J-STD-020)
User I/O Banks — [DATA_NEEDED: user I/O bank count]
User I/O Pins — [DATA_NEEDED: user I/O pin count]
Embedded System Blocks (ESBs) — [DATA_NEEDED: ESB count]
Embedded Array Blocks (EABs) — [DATA_NEEDED: EAB count]
Embedded RAM — [DATA_NEEDED: total bits]
PLLs — [DATA_NEEDED: PLL count]
Configuration Method — JTAG / Passive Serial / Passive Parallel
MSL 等级 — [DATA_NEEDED: MSL level]
RoHS 状态 — [DATA_NEEDED: RoHS compliance]

数据手册与资源

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