EP610DI-25 vs EP610DC-25 对比

详细并排对比 EP610DI-25 出自 Intel 和 EP610DC-25 出自 Rochester Electronics。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Rochester Electronics
EP610DC-25 EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 ✓ 量产中

规格对比

参数 EP610DI-25 EP610DC-25
品牌 Intel Rochester Electronics
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 有效
库存状态 有库存 有库存
单价(USD) $9.95 $9.95
Part Family Classic EPLD —
Macrocells 16 16
Propagation Delay (tPD) 25 ns —
Maximum Pipelined Clock Frequency 100 MHz (max fCNT, per family datasheet) —
I/O Pins 16 (bidirectional) —
Dedicated Inputs 4 —
Total User I/O 20 —
Technology CMOS EPROM (UV-erasable) CMOS EPROM (UV-erasable)
Supply Voltage (VCC) 5 V nominal 4.75 V to 5.25 V (5 V nominal)
Package Type Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 —
引脚数量 24 —
安装类型 Through-Hole (DIP) Through Hole
工作温度 Industrial (per "I" suffix) 0 C to +70 C
Speed Grade Suffix 25 = 25 ns -25 (25 ns tPD)
Compliance RoHS status unknown (legacy 1990s part) —
Family — Altera Classic EPLD
Product Type — EPLD (Erasable Programmable Logic Device)
Equivalent Gates — 300
Maximum Propagation Delay (tPD) — 25 ns
Pipelined Data Rate — Up to 100 MHz
Number of I/O Pins — 22
Number of Dedicated Inputs — 4
Total Pin Count — 24
封装 — 24-pin CDIP (Ceramic DIP, through-hole)
Programming Method — JEDEC fuse-map / UV-erase

数据手册与资源

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