EP910LI-35BF - 24-Macrocell Classic EPLD, 35ns, PLCC-44 | Altera
料号： EP910LI-35BF ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $43.21 | $43.21 |
| 10 | $38.5 | $385.00 |
| 100 | $32.1 | $3,210.00 |
| 500 | $27.4 | $13,700.00 |
| 1,000 | $23.95 | $23,950.00 |
EP910LI-35BF 概述
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple PAL/GAL devices and complex FPGAs in the programmable logic hierarchy (PAL/GAL -> EPLD -> CPLD -> FPGA -> SoC FPGA). It offers erasable/reprogrammable combinational and registered logic, suitable for glue-logic, address decoding, state machines, and bus-interface functions that previously required multiple discrete SSI/MSI TTL parts. EPLDs are characterized by deterministic pin-to-pin timing, a macrocell-based architecture, and predictable routing delays, which is critical for asynchronous and memory-interface designs.
Key features of the EP910LI-35BF include 24 macrocells, 450 usable gates, a maximum pin-to-pin propagation delay (tpd) of 35 ns, a maximum toggle frequency (fmax) of 28.6 MHz, and a 5V supply. The device supports in-system UV-erase (windowed) operation and is packaged in a 44-pin PLCC (J-lead) carrier. Compared with bipolar PAL/GAL devices, the CMOS EP910 offers substantially lower power dissipation, while providing higher integration for logic consolidation.
Internally, the EP910LI-35BF uses a macrocell-based AND/OR array architecture: each macrocell contains a programmable AND-term array, an XOR gate for polarity control, and a flip-flop (D/T/JK/SR selectable). Output enable and feedback are fully programmable, and unused macrocells can be disabled to reduce quiescent current. The device is programmed via a standard EPROM/UV-erase programmer with a 20-pin programming algorithm compatible with the Altera Classic family.
Typical applications include address decoding for 8/16-bit microprocessors and DMA controllers, glue-logic replacement for TTL/CMOS discrete gates, register/latch/FSM consolidation in industrial controllers, bus-interface adapters (e.g., legacy peripheral bus glue), and prototyping platforms where erasability is needed. Because of its 5V supply and TTL compatibility, the EP910 is also used to retrofit older designs that must remain 5V throughout the signal path.
When designing with the EP910LI-35BF, ensure the device is decoded cleanly from other PLDs or memory maps to avoid bus contention, use a 0.1uF decoupling capacitor close to each VCC pin, and respect the IOL/IOH DC specifications (typically 4-8 mA per output) to avoid exceeding drive strength when interfacing to heavily loaded buses.
This page synthesizes distributor pricing, drop-in alternatives, application guidance, and practical design notes not found in the standalone Altera datasheet, including a side-by-side comparison with sibling Classic EP910 speed grades and package options.
直接替换替代料： EP910LI-35BF ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EP910LI-35BF （相同外形与封装尺寸） ——差异在于 Package, Supply Voltage (VCC), Family, Programming Method, Propagation Delay (tPD).
快速对比工具——选择替代料号进行并排对比：
EP910LI-30
✅ 直接替换✓ 有现货
$49.5 / 个
查看数据手册 →EP910LI-30T
✅ 直接替换✓ 有现货
$64.59 / 个
查看数据手册 →EP910LI-25
✅ 直接替换📋 参考替代料（不在目录中）
EP910LC44
✅ 直接替换✓ 有现货
$8.95 / 个
查看数据手册 →EP910LC44-35
✅ 直接替换✓ 有现货
$19.95 / 个
查看数据手册 →EP910LC-35
✅ 直接替换✓ 有现货
$18.75 / 个
查看数据手册 →EP910LI-35BF 最大额定值与电气特性
| Device Family | Altera Classic EPLD |
| Part Number Base | EP910 |
| Logic Density | 450 usable gates |
| Macrocells | 24 |
| Maximum Pin-to-Pin Delay (tpd) | 35 ns |
| Maximum Toggle Frequency (fmax) | 28.6 MHz |
| Supply Voltage (VCC) | 5 V (nominal) |
| 封装 | 44-pin PLCC (J-lead) |
| 工作温度范围 | Industrial (LI suffix) |
| Technology | CMOS, UV-erasable |
| Programming Method | EPROM/UV-erase programmer (Altera Classic algorithm) |
| Output Polarity Control | Programmable XOR per macrocell |
| Flip-Flop Type | Selectable D/T/JK/SR per macrocell |
| TTL Compatibility | 100% TTL emulation |
| Compliance / EOL Status | Obsolete - last-time buy exhausted; second-source via Rochester Electronics |
EP910LI-35BF 引脚配置
| 引脚 1 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 2 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 3 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 4 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 5 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 6 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 7 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 8 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 9 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 10 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 11 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 12 | GND — Ground |
| 引脚 13 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 14 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 15 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 16 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 17 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 18 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 19 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 20 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 21 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 22 | VCC — +5V supply |
| 引脚 23 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 24 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 25 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 26 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 27 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 28 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 29 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 30 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 31 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 32 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 33 | GND — Ground |
| 引脚 34 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 35 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 36 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 37 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 38 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 39 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 40 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 41 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 42 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 43 | I/O — Macrocell I/O (bidirectional, programmable) |
| 引脚 44 | VCC — +5V supply |
典型应用
EP910LI-35BF 适用于 6 应用s: Address Decoding for 8/16-bit Microprocessor Systems, Glue-Logic Replacement / TTL-to-PLD Consolidation, State-Machine and FSM Consolidation, Legacy Peripheral Bus Interface Adapters, Industrial Controller / PLC I/O Expansion, Retrofit / Long-Life-Cycle Medical and Aerospace Equipment.
Address Decoding for 8/16-bit Microprocessor Systems
The EP910LI-35BF is well-suited for address-decoding logic in 8/16-bit microprocessor systems because its 24 macrocells easily handle multi-bank memory or peripheral chip-select decoding. With tpd=35ns and fmax=28.6 MHz, the part comfortably satisfies the access-time budget of microprocessors like the 8086, 68000, or Z80, which typically need sub-50ns CS propagation. The 5V TTL-compatible I/O directly interfaces to the bus without level shifters, and the programmable XOR polarity simplifies active-high vs active-low select generation.
推荐
Glue-Logic Replacement / TTL-to-PLD Consolidation
Engineers commonly replace 4-12 discrete SSI/MSI TTL packages (74LS00, 74LS138, 74LS151, etc.) with a single EP910LI-35BF to reduce board area and improve noise margin. The 450 usable gates comfortably absorb 4-8 SSI functions in one device, while the CMOS technology drops quiescent power by an order of magnitude versus bipolar TTL. The 35ns tpd preserves worst-case timing margins that previously had to be hand-calculated across cascaded TTL gates.
推荐
State-Machine and FSM Consolidation
Each EP910LI-35BF macrocell contains a selectable D/T/JK/SR flip-flop, which makes the device a natural fit for Moore or Mealy finite state machines with up to ~16-20 states. The deterministic pin-to-pin delay (35ns max) simplifies timing closure because every registered output has a guaranteed worst-case clock-to-out independent of placement. Industrial-temperature qualification allows deployment in factory automation and outdoor control cabinets without thermal derating.
推荐
Legacy Peripheral Bus Interface Adapters
The EP910LI-35BF is widely used as a glue device between legacy 5V peripheral buses (ISA, PC/104, STD bus) and modern controllers, acting as a bidirectional bus isolator or level-shift controller. Its 100% TTL compatibility and 5V supply mean no external level translation is needed. Programmable output enable per macrocell simplifies true bidirectional bus handling, while the 24-macrocell capacity is sufficient for 8-16-bit data plus control-signal buffering.
推荐
Industrial Controller / PLC I/O Expansion
The industrial-temperature (-LI-) variant of the EP910 family is rated for -40C to +85C operation, making the EP910LI-35BF a drop-in for I/O expansion logic inside PLCs and industrial controllers. The UV-erasable windowed package supports field firmware updates in legacy installations where ISP is unavailable, and the CMOS process withstands the noisy electrical environment of motor drives with proper decoupling. 24 macrocells can multiplex up to 24 optoisolated inputs or sink 24 relay-driver outputs.
推荐
Retrofit / Long-Life-Cycle Medical and Aerospace Equipment
The EP910LI-35BF is specified in medical-device and aerospace bills-of-material for equipment with 20-30 year service life where re-certification of a new CPLD/FPGA is impractical. Rochester Electronics second-sources the Altera Classic EPLD family for these exact long-life applications. The -LI- industrial temperature window and deterministic timing support functional-safety and DO-254-style verification, while second-source availability mitigates EOL risk over decades of field service.
推荐
推荐产品汇总
工程参考数据： EP910LI-35BF ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EP910LI-30 | EP910LI-25 | EP910LC44-35 | EP910LC-35 | EP910LC44 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 44-pin PLCC (J-lead) | 44-pin PLCC (J-lead) - same | 44-pin PLCC (J-lead) - same | 44-pin PLCC (J-lead) - same | 44-pin PLCC (J-lead) - same | 44-pin PLCC (J-lead) - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 |
| Operating Temperature | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) |
| Supply Voltage | 5V | 5V | 5V | 5V | 5V | 5V |
关键差异点
- Industrial temperature grade in a 5V Classic EPLD （对比 EP910LC-35)
- 35ns speed grade offers design margin for slower buses （对比 EP910LI-30)
- Lead-free / BF finish variant for RoHS-compliant manufacturing （对比 EP910LI-35 (standard finish))
设计说明
The EP910LI-35BF draws quiescent current in the tens-of-mA range and dynamic current proportional to toggle rate; provide a 0.1uF ceramic decoupling capacitor within 5mm of each VCC pin (pins 22 and 44), plus a bulk 10-100uF tantalum on the same 5V rail. Per the Altera Classic datasheet, VCC tolerance is +/-5% (4.75V-5.25V); exceeding this can cause timing-margin violations, especially on the 35ns tpd speed grade.
Place all 24 I/O traces away from analog or noise-sensitive signals; group address/data buses on adjacent pins to simplify PCB routing. The PLCC-44 footprint requires a J-lead socket (e.g., 44-pin PLCC through-hole socket) for prototype debug; production boards can hand-solder but the J-lead pitch is 1.27mm, so stencil/paste and reflow is preferred for volume. Add a ground guard ring around switching outputs if the EP910 is placed near sensitive analog circuitry.
Do not confuse the EP910LI-35BF (PLCC, industrial temp, lead-free finish) with the EP910LC-35 (PLCC, commercial temp) or the EP910LI-30 (faster industrial grade) - they all share the same 44-pin PLCC footprint but differ in speed and temperature grade. Programming the EP910 requires a UV-erasable EPROM programmer with the Altera Classic algorithm; modern programmers often lack this algorithm, so verify programmer support before committing to the EP910 for new designs. Finally, because the part is obsolete, second-source only via Rochester Electronics or wafer-bank inventory.
Pin 1 of the PLCC-44 is at the top-left when the package is viewed from above with the chamfer/orientation dot visible; keep at least a 2mm keepout under the PLCC socket for the erase-window model variant. Use a star-ground topology from the EP910 to the system ground if the design includes both analog and digital grounds; otherwise a unified ground plane with cut-outs under switching I/O pins is acceptable. Place programming-pin access on the board edge if in-system UV erase is required for field firmware updates.
合规信息
RoHS compliant per -BF finish suffix. Reach SVHC declaration available from Rochester Electronics on request. AEC-Q100 not applicable - this is a generic EPLD, not an automotive-grade part. Lead-free (-BF) finish confirmed; halogen-free status not stated in the Altera Classic datasheet excerpt. Conflict-minerals declaration per Altera (Intel PSG) standard policy.