EP910PI-15T vs EP910PI-12T 对比
详细并排对比 EP910PI-15T 出自 Altera 和 EP910PI-12T 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910PI-15T | EP910PI-12T |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.95 | $9.95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP910 series) | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| 电源电压 | 4.5 V to 5.5 V (5 V nominal) | — |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | 12 ns |
| Technology | CMOS EEPROM (electrically erasable) | — |
| 封装 | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | 40-pin PDIP (Plastic DIP) |
| 安装类型 | Through-Hole | — |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| 工作温度 | [DATA_NEEDED: industrial/commercial temp range] | 0C to +70C (commercial) |
| Programming | JEDEC-standard, serial/parallel programmer | — |
| RoHS 状态 | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | Non-compliant (legacy PDIP package, contains lead) |
| Maximum Operating Frequency | — | 76.9 MHz |
| Logic Gates | — | [DATA_NEEDED: logic gate count] |
| Supply Voltage (VCC) | — | 5 V (4.75 V min, 5.25 V max) |
| External Clock Inputs | — | 2 |
| Outputs | — | 24 |
| Terminals / Pin Count | — | 44 (PDIP-40 package pinout with NC pins) |
| Process Technology | — | CMOS |
| Programmable Technology | — | UV-erasable EPROM |
| Programming Interface | — | JEDEC-standard |
| 生命周期状态 | — | NRND / EOL (mature legacy product) |