EPC2LC20N-W vs EPC2CC20N 对比

详细并排对比 EPC2LC20N-W 出自 Altera 和 EPC2CC20N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC2LC20N-W EPC2CC20N
品牌 Altera Altera
分类 Memory ICs FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $6.45 $10.85
存储器类型 EPROM (UV-erasable, ISP) —
存储容量 1.6 Mbit —
Programmable Type In System Programmable —
Configuration Interface Serial (DATA, DCLK, OE, nCS) 16-bit parallel (FPP) / Passive Serial (PS)
Internal Oscillator Frequency 66.7 MHz —
Supply Voltage (VCC) 3.0 V to 3.6 V, 4.75 V to 5.25 V 3.3 V
ISP Interface JTAG (IEEE 1149.1) —
Supported FPGA Families APEX 20K, ACEX 1K, Mercury, FLEX 10K, Stratix, Cyclone —
封装 20-LCC (J-Lead) PLCC-20 PLCC-20
安装类型 Surface Mount Surface Mount (PLCC-20 socket compatible)
Packaging Tape & Reel (-W suffix) —
Cascade Support Yes (with other EPC2 devices) —
引脚数量 20 —
Lead-Free / RoHS [DATA_NEEDED: RoHS status for -W variant] —
工作温度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: industrial/commercial temp range]
功能 — Configuration device for SRAM-based LUT FPGAs
Density — [DATA_NEEDED: bitstream density in bits]
Programming Interface — JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster
In-System Programmable — Yes
Error Detection — 16-bit CRC on configuration frames
Configuration Modes Supported — FPP and PS (depends on host FPGA)
Cascadable — Yes (multiple EPC2 devices for larger bitstreams)
Open-Drain Status Pin — Yes (CONF_DONE / nSTATUS compatible)
MSL 等级 — [DATA_NEEDED: MSL rating]
RoHS 状态 — [DATA_NEEDED: RoHS compliance status]

数据手册与资源

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