EPC2LC20N-W vs EPC2CC20N Comparison
Detailed side-by-side comparison of EPC2LC20N-W by Altera and EPC2CC20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2LC20N-W | EPC2CC20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Memory Type | EPROM (UV-erasable, ISP) | — |
| Memory Size | 1.6 Mbit | — |
| Programmable Type | In System Programmable | — |
| Configuration Interface | Serial (DATA, DCLK, OE, nCS) | 16-bit parallel (FPP) / Passive Serial (PS) |
| Internal Oscillator Frequency | 66.7 MHz | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V, 4.75 V to 5.25 V | 3.3 V |
| ISP Interface | JTAG (IEEE 1149.1) | — |
| Supported FPGA Families | APEX 20K, ACEX 1K, Mercury, FLEX 10K, Stratix, Cyclone | — |
| Package | 20-LCC (J-Lead) PLCC-20 | PLCC-20 |
| Mounting Type | Surface Mount | Surface Mount (PLCC-20 socket compatible) |
| Packaging | Tape & Reel (-W suffix) | — |
| Cascade Support | Yes (with other EPC2 devices) | — |
| Pin Count | 20 | — |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS status for -W variant] | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temp range] |
| Function | — | Configuration device for SRAM-based LUT FPGAs |
| Density | — | [DATA_NEEDED: bitstream density in bits] |
| Programming Interface | — | JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster |
| In-System Programmable | — | Yes |
| Error Detection | — | 16-bit CRC on configuration frames |
| Configuration Modes Supported | — | FPP and PS (depends on host FPGA) |
| Cascadable | — | Yes (multiple EPC2 devices for larger bitstreams) |
| Open-Drain Status Pin | — | Yes (CONF_DONE / nSTATUS compatible) |
| MSL Level | — | [DATA_NEEDED: MSL rating] |
| RoHS Status | — | [DATA_NEEDED: RoHS compliance status] |