EPC8QC100 vs EPC2TC32V 对比

详细并排对比 EPC8QC100 出自 Altera 和 EPC2TC32V 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC8QC100 EPC2TC32V
品牌 Altera Altera
分类 Memory ICs Memory ICs
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $17.50 $9.20
存储器类型 Configuration PROM (Flash-based) In-System Programmable Configuration PROM
存储容量 8 Mbit 1.6 Mbit
Flash Access Time 90 ns (~10 MHz) —
Configuration Bus Width 16-bit (DQ[]) —
Configuration Bandwidth Up to 160 Mbps —
Decompression Support Yes (Altera proprietary) —
Supported Configuration Modes FPP, PS, AS (FPGA-dependent) —
ISP Interface JTAG (IEEE 1149.1) —
电源电压 3.3 V —
工作温度 0C to +70C (Commercial) 0 C to +70 C (commercial)
封装 100-Pin PQFP (20 x 14 mm) 32-pin TQFP (7 mm x 7 mm)
安装类型 Surface Mount Surface Mount
Compatible FPGA Families Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K APEX 20K, APEX II, FLEX 10K/10KE, ACEX 1K, Cyclone (original), Stratix (original)
RoHS 状态 [DATA_NEEDED: RoHS compliance] Compliant
Lead Free [DATA_NEEDED: lead-free status] —
存储组织 — x8 (configurable serial/parallel output)
Supply Voltage (VCC) — 3.0 V to 3.6 V (3.3 V nominal)
I/O Voltage Tolerance — 5 V tolerant
接口 — Passive Serial (PS), Passive Parallel Async (PPA), Passive Parallel Sync (PPS), JTAG ISP
Programming Method — In-system via JTAG (IEEE 1149.1)
Cascadable — Yes (multiple EPC2s daisy-chain for larger bitstreams)
MSL 等级 — [DATA_NEEDED: MSL level]
Configuration Hand-shake Pins — nCONFIG, nSTATUS, CONF_DONE, DCLK
Lead-Free — Yes

数据手册与资源

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