EPM3128ATC100-5 vs EPM3128ATC144-5 对比

详细并排对比 EPM3128ATC100-5 出自 Intel 和 EPM3128ATC144-5 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3128ATC100-5 EPM3128ATC144-5
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $15.43 $4.85
Series MAX 3000A —
Family CPLD - MAX 3000A MAX 3000A
Macrocells 128 —
Usable Gates 2,500 —
User I/Os 80 —
Dedicated Inputs 4 —
Pin-to-Pin Delay (tpd) 5 ns (commercial); 7.5 ns —
Maximum Frequency (fCNT) 192.3 MHz —
Supply Voltage (VCCINT/VCCIO) 3.3 V —
Output Drive Voltage 2.5 V or 3.3 V (programmable) —
Input Tolerance 2.5 V, 3.3 V, 5.0 V tolerant —
Program Memory Type EEPROM EEPROM (non-volatile)
In-System Programmability Yes, IEEE Std. 1532 compliant Yes (IEEE Std. 1532 compliant)
JTAG Boundary Scan Yes, IEEE Std. 1149.1 —
工作温度 0 °C to 70 °C (Commercial) 0C to +70C (Commercial)
封装 100-pin TQFP (Fine Line) TQFP-144 (Plastic, 1.0 mm pitch, 22x22 mm)
安装类型 Surface Mount —
Logic Family CMOS CMOS
RoHS 状态 [DATA_NEEDED: RoHS status] Not Compliant (per Arrow distributor listing)
Process Technology CMOS EEPROM 0.30 um CMOS EEPROM, 4 metal layers
Device Type — CPLD (Complex Programmable Logic Device)
Number of Macrocells — 128
Number of Logic Array Blocks (LABs) — 8
Number of User I/Os — 96
Device System Gates — 2500
Product Terms per Macrocell — 32
Propagation Delay (tPD) — 7.5 ns
Maximum Internal Frequency — 192.3 MHz
Number of Global Clocks — 2
Supply Voltage (Core) — 3.3 V
Multi-Volt I/O Voltage — 2.5 V / 3.3 V / 5.0 V tolerant
JTAG / IEEE 1149.1 — Yes (boundary-scan + ISP)
ECCN — EAR99
HTS Code — 8542.31.00.55

数据手册与资源

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