EPM3512AFC256-3N vs EPM3512AFC256-7 对比
详细并排对比 EPM3512AFC256-3N 出自 Altera 和 EPM3512AFC256-7 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EPM3512AFC256-7 - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel
EPM3512AFC256-7 ⚠ 最后一次采购规格对比
| 参数 | EPM3512AFC256-3N | EPM3512AFC256-7 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $23.40 | $58.40 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum Operating Frequency | 116.3 MHz | — |
| Pin-to-Pin Delay (tPD) | 3.5 ns (speed grade -3) | — |
| Speed Grade | -3 (slowest in family) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| 封装 | 256-ball FineLine BGA (FC-256) | 256-ball FineLine BGA (FBGA-256) |
| 安装类型 | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP | — |
| Configuration Memory | Non-volatile EEPROM | Non-volatile EEPROM |
| 工作温度 | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature grade] |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| User I/O Pins | — | 212 |
| Pin-to-Pin Logic Delay | — | 7.5 ns |
| Counter Frequency (max) | — | 227.3 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typ.) |
| I/O Voltage (VCCIO) | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Programming | — | EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant) |