EPM5032LC-20 vs EPM5032JC-20 对比

详细并排对比 EPM5032LC-20 出自 Altera 和 EPM5032JC-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5032LC-20 EPM5032JC-20
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $8.40 $9.75
Device Family MAX 5000 —
Product Type EPLD / CPLD (One-Time Programmable / UV-Erasable) UV-erasable Programmable Logic Device (PLD)
Usable Gates 600 gates —
Macrocells 32 32
Logic Blocks (LABs) 1 —
Speed Grade -20 (20 ns pin-to-pin) —
Maximum Frequency 71.4 MHz —
Propagation Delay (tPD) 20 ns 20 ns
Supply Voltage (VCC) 5 V ±5% —
工作温度 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) —
Dedicated Inputs 7 8
Bidirectional I/O Pins 16 —
Total Inputs 24 24
Output Functions 16 —
Product Terms per Output 16 —
Programmable Interconnect Programmable Interconnect Array (PIA) —
封装 LCC-28 (Plastic Leaded Chip Carrier, J-lead) 68-pin JLCC (windowed ceramic)
安装类型 Surface Mount —
RoHS 状态 [DATA_NEEDED: RoHS status] —
MSL 等级 [DATA_NEEDED: MSL] —
Family — MAX 5000
Logic Array Blocks (LABs) — 1
Product Terms (P-terms) — 320
最大时钟频率 — 62.5 MHz
Setup Time — 10 ns
I/O Lines — 16 (bidirectional)
Process Technology — CMOS
Erase Method — UV (12V VPP + ultraviolet exposure)
Programming Voltage (VPP) — 12 V
Architecture — PAL-type AND-OR array with PIA interconnect
生命周期状态 — Obsolete (legacy Altera MAX 5000)

数据手册与资源

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