EPM5032LC-20 vs EPM5032JC-20 Comparison

Detailed side-by-side comparison of EPM5032LC-20 by Altera and EPM5032JC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5032LC-20

EPM5032LC-20 - 32-Macrocell MAX 5000 CPLD, 20ns, LCC-28 | Altera

EPM5032LC-20 Obsolete
Altera
EPM5032JC-20

EPM5032JC-20 - 32-Macrocell UV PLD, 20ns, 24 Inputs | Altera

EPM5032JC-20 Obsolete

Specification Comparison

Parameter EPM5032LC-20 EPM5032JC-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.40 $9.75
Device Family MAX 5000 β€”
Product Type EPLD / CPLD (One-Time Programmable / UV-Erasable) UV-erasable Programmable Logic Device (PLD)
Usable Gates 600 gates β€”
Macrocells 32 32
Logic Blocks (LABs) 1 β€”
Speed Grade -20 (20 ns pin-to-pin) β€”
Maximum Frequency 71.4 MHz β€”
Propagation Delay (tPD) 20 ns 20 ns
Supply Voltage (VCC) 5 V Β±5% β€”
Operating Temperature 0 Β°C to +70 Β°C (commercial; -55 Β°C to +125 Β°C military per /883B variants) β€”
Dedicated Inputs 7 8
Bidirectional I/O Pins 16 β€”
Total Inputs 24 24
Output Functions 16 β€”
Product Terms per Output 16 β€”
Programmable Interconnect Programmable Interconnect Array (PIA) β€”
Package LCC-28 (Plastic Leaded Chip Carrier, J-lead) 68-pin JLCC (windowed ceramic)
Mounting Type Surface Mount β€”
RoHS Status [DATA_NEEDED: RoHS status] β€”
MSL Level [DATA_NEEDED: MSL] β€”
Family β€” MAX 5000
Logic Array Blocks (LABs) β€” 1
Product Terms (P-terms) β€” 320
Maximum Clock Frequency β€” 62.5 MHz
Setup Time β€” 10 ns
I/O Lines β€” 16 (bidirectional)
Process Technology β€” CMOS
Erase Method β€” UV (12V VPP + ultraviolet exposure)
Programming Voltage (VPP) β€” 12 V
Architecture β€” PAL-type AND-OR array with PIA interconnect
Lifecycle Status β€” Obsolete (legacy Altera MAX 5000)

Datasheets & Resources

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