EPM5128JC-1 vs EPM5128JC 对比

详细并排对比 EPM5128JC-1 出自 Altera 和 EPM5128JC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5128JC-1 EPM5128JC
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $24.95 $9.75
Family MAX 5000 —
Device Type Erasable Programmable Logic Device (EPLD/CPLD) EPLD / CPLD
Macrocells 128 —
Usable Gates 2,500 —
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] —
Maximum Operating Frequency 62.5 MHz —
Pin-to-Pin Propagation Delay (tPD) 40 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (typical)
Technology CMOS, UV-erasable EPROM —
封装 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) —
安装类型 Surface Mount Surface Mount (PLCC socket or solder)
工作温度 [DATA_NEEDED: temperature grade] Commercial 0C to +70C
Programming Interface JTAG / Altera dedicated programmer Altera MAX+PLUS II / A+PLUS / legacy programmer
Configuration Memory Non-volatile EPROM (UV-erasable) UV-erasable EPROM (windowed package)
RoHS 状态 non_compliant (ceramic windowed package) [DATA_NEEDED: RoHS status - legacy part]
生命周期状态 Obsolete - last-time-buy inventory only —
Product Family — MAX 5000
Macrocell Count — 128
Propagation Delay (tPD) — 35 ns
Logic Elements — Programmable AND/OR/XOR array
引脚数 — 68
Package Type — PLCC-68 (JLCC) ceramic, J-leaded
Dedicated Inputs — 8
User I/O Pins — [DATA_NEEDED: user I/O pin count]
Boundary Scan — JTAG IEEE 1149.1 (family feature)
Process Technology — CMOS EPROM
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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