EPM5192AJC84-20 vs EPM5192AJC-25 对比
详细并排对比 EPM5192AJC84-20 出自 Altera 和 EPM5192AJC-25 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 Obsolete
规格对比
| 参数 | EPM5192AJC84-20 | EPM5192AJC-25 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $19.20 | $8.20 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | UV-erasable/OTP Complex PLD (CPLD) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 33 ns (speed grade -20) | — |
| 最大时钟频率 | 66.7 MHz | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V | — |
| Dedicated Inputs | 7 | — |
| User I/O Lines | 64 | — |
| Process Technology | CMOS, UV-erasable EEPROM | — |
| 封装 | 84-pin PLCC J-Lead (WQCCJ, J84) | PLCC-68 (windowed ceramic, AJC) |
| Operating Temperature Grade | Commercial | — |
| 安装类型 | Surface Mount (J-Lead) | Surface Mount |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Programming Tool | Altera MAX+PLUS II / Quartus (legacy) | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Propagation Delay (tPD) | — | 25 ns |
| 引脚数量 | — | 68 |
| 电源电压 | — | 5 V (typical) |
| Logic Blocks | — | MAX 5000 LABs (Logic Array Blocks) |
| Programmable Pins | — | [DATA_NEEDED: number of user I/O pins] |
| 工作温度 | — | [DATA_NEEDED: exact operating temperature range] |
| Erasure Method | — | UV-erasable (windowed ceramic package) |
| Programming Technology | — | EPROM (non-volatile) |
| Military Grade | — | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) |