EPM5192AJI84-15 vs EPM5192ALI84-15 对比

详细并排对比 EPM5192AJI84-15 出自 Altera 和 EPM5192ALI84-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192AJI84-15 EPM5192ALI84-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $27.80 $9.95
Device Family MAX 5000 EPLD MAX 5000
Product Type UV-Erasable / OTP Complex PLD UV-Erasable / OTP Complex PLD
Macrocells 192 —
Logic Array Blocks (LABs) 16 —
User I/O Pins 84 —
Propagation Delay (tPD) 15 ns 25 ns (-15 speed grade)
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) —
Process Technology CMOS EPROM (UV-erasable) CMOS, non-volatile EPROM/OTP
Package Type 84-pin JLCC (J-Leaded Ceramic Chip Carrier) with quartz window —
安装类型 Through-Hole (SMD socket-compatible) Surface Mount (PLCC socket compatible)
工作温度 -40 °C to +85 °C (Industrial, 'I' suffix) —
Programming Method UV erase + EPROM program via standard Altera programmer —
Design Tool Support MAX+PLUS II (legacy); not supported by modern Quartus Prime —
RoHS 状态 unknown [DATA_NEEDED: RoHS status]
Lead-Free unknown —
无卤 unknown —
Functional Equivalent (Plastic OTP) EPM5192AJC84-15 (windowless plastic JLCC, same die) —
Logic Macrocells — 192
Dedicated Inputs — 7
Bidirectional I/O Pins — 64
Maximum Total Inputs — 72
Programmability — One-Time Programmable (windowless)
封装 — 84-pin PQCC (PLCC, J-Lead)
JEDEC JESD-30 Code — S-PQCC-J84
Terminal Form — J Bend (J-Lead)
Operating Temperature Grade — Industrial
工作温度范围 — [DATA_NEEDED: temperature range]
电源电压 — [DATA_NEEDED: VCC range]

数据手册与资源

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