EPM5192JC-ES vs EPM5192JC68 对比
详细并排对比 EPM5192JC-ES 出自 Intel 和 EPM5192JC68 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5192JC-ES | EPM5192JC68 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $16.45 | $15.85 |
| Device Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (EPLD) | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | UV-Erasable EPROM |
| 封装 | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | — |
| 安装类型 | Surface Mount | Surface Mount (PLCC socket compatible) |
| Technology | CMOS | — |
| Programming | Altera MAX+PLUS II or compatible programmer | — |
| 工作温度 | [DATA_NEEDED: operating temperature range for ES grade] | 0C to 70C (commercial, JC suffix) |
| 电源电压 | [DATA_NEEDED: VCC nominal] | [DATA_NEEDED: VCC] |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | 76 |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 等级 | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Elements / Macrocells | — | 192 macrocells |
| 引脚数 | — | 68 |
| Package Type | — | PLCC-68 (J-Lead) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX] |
| Programmable Interconnect | — | Programmable Logic Array + Macrocells |
| Dedicated Inputs | — | 12 |
| Clock Pins | — | 4 dedicated |
| Programming Tool | — | MAX+PLUS II (legacy) |