EPM5192JC-ES vs EPM5192JC68 Comparison
Detailed side-by-side comparison of EPM5192JC-ES by Intel and EPM5192JC68 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JC-ES | EPM5192JC68 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Device Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (EPLD) | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | UV-Erasable EPROM |
| Package | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | — |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket compatible) |
| Technology | CMOS | — |
| Programming | Altera MAX+PLUS II or compatible programmer | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range for ES grade] | 0C to 70C (commercial, JC suffix) |
| Supply Voltage | [DATA_NEEDED: VCC nominal] | [DATA_NEEDED: VCC] |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | 76 |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL Level | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Elements / Macrocells | — | 192 macrocells |
| Number of Pins | — | 68 |
| Package Type | — | PLCC-68 (J-Lead) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX] |
| Programmable Interconnect | — | Programmable Logic Array + Macrocells |
| Dedicated Inputs | — | 12 |
| Clock Pins | — | 4 dedicated |
| Programming Tool | — | MAX+PLUS II (legacy) |