EPM9320ALC84-15 vs EPM9320ALC84-20 对比

详细并排对比 EPM9320ALC84-15 出自 Altera 和 EPM9320ALC84-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9320ALC84-15 EPM9320ALC84-20
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $9.95 $10.50
Family MAX 9000 CPLD MAX 9000
Macrocells 320 320
Usable Gates 6000 —
Propagation Delay (tPD) 16 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
User I/O 56 —
Logic Array Blocks (LABs) 16 16
Technology CMOS, EEPROM-based configuration —
封装 84-pin PLCC (S-PQCC-J84, J-lead) PLCC-84
安装类型 Through-hole / socket Surface Mount (PLCC socket compatible)
Programming Interface JTAG (IEEE 1149.1) / ISP —
工作温度 -40C to +85C (industrial) [DATA_NEEDED: commercial or industrial grade]
RoHS 状态 [DATA_NEEDED: rohs status] [DATA_NEEDED: per Altera datasheet]
湿敏等级(MSL) MSL-3 (168 hours per fpgalink.com) —
Lead-Free / Halogen-Free [DATA_NEEDED: lead free status] —
RoHS3 Compliance ROHS3 Compliant (per fpgalink.com listing) —
Device Type — EPLD (Erasable Programmable Logic Device)
Maximum User I/Os — 212
Pin-to-Pin Delay (tPD) — 20 ns
Process Technology — 0.5 µm CMOS EEPROM
电源电压 — 5.0 V
Programmability — In-system via IEEE 1149.1 JTAG
Configuration Memory — Non-volatile EEPROM
Boundary Scan — JTAG IEEE 1149.1
Design Software — MAX+PLUS II / Quartus II (legacy)

数据手册与资源

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