EPM9320RC208-20 vs EPM9320GC280-20 对比
详细并排对比 EPM9320RC208-20 出自 Altera 和 EPM9320GC280-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9320RC208-20 | EPM9320GC280-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $21.90 | $67.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | 20 (16 macrocells each, typical for MAX 9000) |
| Usable Gates | 6,000 | 6000 (approx.) |
| Maximum I/O Pins | 132 | — |
| Propagation Delay (tPD max) | 20 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Programming Technology | EEPROM, in-system programmable (ISP) | — |
| Boundary-Scan Interface | IEEE Std. 1149.1 (JTAG) | — |
| 工作温度 | 0 °C to 70 °C (commercial) | [DATA_NEEDED: operating temperature grade] |
| 封装 | 208-RQFP, exposed pad (208-BFQFP) | 280-pin Ceramic Pin Grid Array (CPGA) |
| 安装类型 | Surface Mount | Through-Hole (PGA socket) |
| Architecture | Multiple Array Matrix (MAX), 3rd generation | — |
| Process Technology | CMOS, 5.0 V EEPROM | — |
| Reprogrammability | Yes, unlimited ISP cycles | — |
| Maximum Operating Frequency | — | 100 MHz (internal counter) |
| Propagation Delay (tpd) | — | 23 ns (approx., -20 speed grade) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (5.0-V ISP via JTAG) |
| JTAG Support | — | IEEE Std. 1149.1 compliant |
| RoHS 状态 | — | unknown |
| Configuration Memory | — | EEPROM (non-volatile, instant-on) |