EPM9400LC84-20 vs EPM9320LC84-20 对比

详细并排对比 EPM9400LC84-20 出自 Altera 和 EPM9320LC84-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9400LC84-20 EPM9320LC84-20
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $38.50 $9.75
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Architecture Multiple Array Matrix (MAX), 3rd generation, EEPROM-based Multiple Array MatriX (MAX), 3rd generation
Macrocells 400 320
Usable Gates 8,000 (6,000 to 12,000 typical range) —
Flip-Flops 580 —
Maximum User I/O 55 —
Pin-to-Pin Propagation Delay 20 ns (speed grade -20) —
Maximum Counter Frequency 144 MHz —
Supply Voltage (VCCINT) 5 V —
I/O Voltage (VCCIO) 3.3 V or 5 V (configurable) —
In-System Programming Yes (IEEE 1149.1 JTAG) —
封装 84-pin PLCC (Plastic Leaded Chip Carrier) PLCC-84 (Plastic Leaded Chip Carrier)
Process Technology CMOS EEPROM —
工作温度 Commercial (0C to +70C) - assumed from -20 speed grade 0 C to 70 C
安装类型 Surface Mount (PLCC socket or SMT land pattern) —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
User I/Os — 60
Logic Family — CMOS (EEPROM-based)
Pins — 84
Propagation Delay (tPD) — 16 ns
Internal Counter Frequency — 118 MHz
电源电压 — 5.0 V
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Dedicated Inputs — 4 (global clock / clear / OE)
PCI Compliance — PCI Local Bus Specification Rev. 2.2

数据手册与资源

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