EPM9400LC84-20 vs EPM9320LC84-20 Comparison
Detailed side-by-side comparison of EPM9400LC84-20 by Altera and EPM9320LC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9400LC84-20 | EPM9320LC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Architecture | Multiple Array Matrix (MAX), 3rd generation, EEPROM-based | Multiple Array MatriX (MAX), 3rd generation |
| Macrocells | 400 | 320 |
| Usable Gates | 8,000 (6,000 to 12,000 typical range) | — |
| Flip-Flops | 580 | — |
| Maximum User I/O | 55 | — |
| Pin-to-Pin Propagation Delay | 20 ns (speed grade -20) | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (configurable) | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) | PLCC-84 (Plastic Leaded Chip Carrier) |
| Process Technology | CMOS EEPROM | — |
| Operating Temperature | Commercial (0C to +70C) - assumed from -20 speed grade | 0 C to 70 C |
| Mounting Type | Surface Mount (PLCC socket or SMT land pattern) | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| User I/Os | — | 60 |
| Logic Family | — | CMOS (EEPROM-based) |
| Pins | — | 84 |
| Propagation Delay (tPD) | — | 16 ns |
| Internal Counter Frequency | — | 118 MHz |
| Supply Voltage | — | 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Dedicated Inputs | — | 4 (global clock / clear / OE) |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 |