EPM9400LC84-20 vs EPM9400LC84-15 对比
详细并排对比 EPM9400LC84-20 出自 Altera 和 EPM9400LC84-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9400LC84-20 | EPM9400LC84-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $38.50 | $23.10 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array Matrix (MAX), 3rd generation, EEPROM-based | — |
| Macrocells | 400 | — |
| Usable Gates | 8,000 (6,000 to 12,000 typical range) | 8,000 |
| Flip-Flops | 580 | — |
| Maximum User I/O | 55 | — |
| Pin-to-Pin Propagation Delay | 20 ns (speed grade -20) | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (configurable) | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| 封装 | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC |
| Process Technology | CMOS EEPROM | — |
| 工作温度 | Commercial (0C to +70C) - assumed from -20 speed grade | 0C to +70C (Commercial) |
| 安装类型 | Surface Mount (PLCC socket or SMT land pattern) | Surface Mount |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 400 |
| Logic Array Blocks | — | 25 |
| Maximum User I/Os | — | 59 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Speed Grade | — | -15 (15 ns pin-to-pin delay) |
| Core Supply Voltage (VCCINT) | — | 5.0 V |
| Input Logic Compatibility | — | TTL, 3.3 V and 5.0 V tolerant |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant (ISP) |
| Minimum VCCINT | — | 4.75 V |
| Programming Method | — | In-System Programmable via JTAG |