EPM9400LC84-20 vs EPM9400LC84-15 Comparison

Detailed side-by-side comparison of EPM9400LC84-20 by Altera and EPM9400LC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9400LC84-20 EPM9400LC84-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $38.50 $23.10
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multiple Array Matrix (MAX), 3rd generation, EEPROM-based β€”
Macrocells 400 β€”
Usable Gates 8,000 (6,000 to 12,000 typical range) 8,000
Flip-Flops 580 β€”
Maximum User I/O 55 β€”
Pin-to-Pin Propagation Delay 20 ns (speed grade -20) β€”
Maximum Counter Frequency 144 MHz β€”
Supply Voltage (VCCINT) 5 V β€”
I/O Voltage (VCCIO) 3.3 V or 5 V (configurable) β€”
In-System Programming Yes (IEEE 1149.1 JTAG) β€”
Package 84-pin PLCC (Plastic Leaded Chip Carrier) 84-pin PLCC
Process Technology CMOS EEPROM β€”
Operating Temperature Commercial (0C to +70C) - assumed from -20 speed grade 0C to +70C (Commercial)
Mounting Type Surface Mount (PLCC socket or SMT land pattern) Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Macro Cells β€” 400
Logic Array Blocks β€” 25
Maximum User I/Os β€” 59
Maximum Operating Frequency β€” 117.6 MHz
Speed Grade β€” -15 (15 ns pin-to-pin delay)
Core Supply Voltage (VCCINT) β€” 5.0 V
Input Logic Compatibility β€” TTL, 3.3 V and 5.0 V tolerant
Configuration Memory β€” EEPROM (non-volatile, in-system programmable)
JTAG Interface β€” IEEE Std. 1149.1 compliant (ISP)
Minimum VCCINT β€” 4.75 V
Programming Method β€” In-System Programmable via JTAG

Datasheets & Resources

Browse All Products Create BOM Request Quote