EPM9400LC84-20 vs EPM9400LC84-15 比較
詳細な並列比較: EPM9400LC84-20 メーカー: Altera および EPM9400LC84-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9400LC84-20 | EPM9400LC84-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $38.50 | $23.10 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array Matrix (MAX), 3rd generation, EEPROM-based | — |
| Macrocells | 400 | — |
| Usable Gates | 8,000 (6,000 to 12,000 typical range) | 8,000 |
| Flip-Flops | 580 | — |
| Maximum User I/O | 55 | — |
| Pin-to-Pin Propagation Delay | 20 ns (speed grade -20) | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (configurable) | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| パッケージ | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC |
| Process Technology | CMOS EEPROM | — |
| 動作温度 | Commercial (0C to +70C) - assumed from -20 speed grade | 0C to +70C (Commercial) |
| 実装タイプ | Surface Mount (PLCC socket or SMT land pattern) | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 400 |
| Logic Array Blocks | — | 25 |
| Maximum User I/Os | — | 59 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Speed Grade | — | -15 (15 ns pin-to-pin delay) |
| Core Supply Voltage (VCCINT) | — | 5.0 V |
| Input Logic Compatibility | — | TTL, 3.3 V and 5.0 V tolerant |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant (ISP) |
| Minimum VCCINT | — | 4.75 V |
| Programming Method | — | In-System Programmable via JTAG |