EPM9560RC208-21 vs EPM9560RC208-15 对比

详细并排对比 EPM9560RC208-21 出自 Intel 和 EPM9560RC208-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC208-21 EPM9560RC208-15
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $22.95 $0.00
Family MAX 9000 MAX 9000
Architecture Multiple Array MatriX (MAX), third-generation Third-generation Multiple Array MatriX (MAX)
Technology CMOS EEPROM-based —
Macrocells 560 —
Usable Gates 12,000 12,000 gates
Logic Array Blocks (LABs) 16 —
Flip-Flops 772 —
Maximum User I/O 149 —
Propagation Delay (speed grade -21) 21 ns (max, per speed grade designation) —
电源电压 5.0 V 5.0 V
I/O Voltage Tolerance 3.3 V or 5 V (per variant) —
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) Yes, via IEEE Std. 1149.1 JTAG
封装 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
工作温度 [DATA_NEEDED: industrial or commercial grade -21 suffix] [DATA_NEEDED: operating temperature range]
Configuration Memory EEPROM (non-volatile) —
Security Bit Yes (programmable) —
RoHS 状态 [DATA_NEEDED: confirm RoHS compliance for -21 variant] [DATA_NEEDED: RoHS status]
Device Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Macro Cells — 560 macro cells
Pin-to-Pin Delay — 15 ns
Counter Speed — 117.6 MHz
Configuration Technology — EEPROM (non-volatile)
安装类型 — Surface Mount
Number of I/O Pins — [DATA_NEEDED: number of I/O pins]
Logic Array Blocks — [DATA_NEEDED: number of logic array blocks]
Speed Grade — -15 (15 ns pin-to-pin)

数据手册与资源

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