EPM9560RC208-21 vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RC208-21 by Intel and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RC208-21 - MAX 9000 CPLD, 560 Macrocells, 208-Pin RQFP | Intel (Altera)
EPM9560RC208-21 ⚠ Last Time BuySpecification Comparison
| Parameter | EPM9560RC208-21 | EPM9560RC208-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX), third-generation | Third-generation Multiple Array MatriX (MAX) |
| Technology | CMOS EEPROM-based | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 16 | — |
| Flip-Flops | 772 | — |
| Maximum User I/O | 149 | — |
| Propagation Delay (speed grade -21) | 21 ns (max, per speed grade designation) | — |
| Supply Voltage | 5.0 V | 5.0 V |
| I/O Voltage Tolerance | 3.3 V or 5 V (per variant) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | Yes, via IEEE Std. 1149.1 JTAG |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Operating Temperature | [DATA_NEEDED: industrial or commercial grade -21 suffix] | [DATA_NEEDED: operating temperature range] |
| Configuration Memory | EEPROM (non-volatile) | — |
| Security Bit | Yes (programmable) | — |
| RoHS Status | [DATA_NEEDED: confirm RoHS compliance for -21 variant] | [DATA_NEEDED: RoHS status] |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| Mounting Type | — | Surface Mount |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |