5962L0423003VXC - 14-Bit 80MSPS ADC | MIL-PRF-38535 Class V | ADI
料号： 5962L0423003VXC ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
5962L0423003VXC 概述
An analog-to-digital converter (ADC) is a data-conversion integrated circuit that converts a continuous analog input voltage or current into a discrete digital code proportional to the input magnitude. ADCs sit in the data-acquisition signal chain between the analog front end (amplifiers, filters, mixers) and the digital processor (FPGA, DSP, ASIC). Architectural variants include successive-approximation register (SAR), pipeline, flash, sigma-delta, and integrating converters; pipeline ADCs such as the 5962L0423003VXC dominate the 10 MSPS to 250 MSPS mid-speed segment where both sample rate and dynamic range matter. In the broader component taxonomy, the ADC belongs to the data-converter family, itself a subset of signal-conditioning and mixed-signal ICs under the broader power-management and analog-IC hierarchy.
Key features of the 5962L0423003VXC include 14-bit resolution, 80 MHz minimum sample rate, dual 3.3 V/5 V analog supply, single 3.3 V or 5 V digital supply, integrated input buffer and track-and-hold, and LVDS/CMOS-compatible digital outputs. The -55 °C to +125 °C operating-temperature range and radiation-hardened-by-design construction (per the 5962 prefix SMD) make it appropriate for harsh-environment deployments.
The internal architecture is based on a multi-stage pipeline core with proprietary input buffering that maintains distortion performance beyond 200 MHz IF. The hermetic ceramic TQFP-EP package (52 terminals) supports lead-bearing or lead-free finishes, with the EP providing a low-thermal-resistance path for high-temperature derating. On-chip dithering and gain trim yield consistent spurious-free dynamic range (SFDR) across lots, which is critical in radar and electronic-warfare receivers where repeatability under mission profile matters more than absolute best-case numbers.
Typical applications include military radar receivers, electronic-countermeasures (ECM) front ends, software-defined radio (SDR) IF digitizers, satellite-communications (SATCOM) modems, and high-temperature industrial telemetry. The dual-supply topology simplifies interface to legacy 5 V analog signal chains still common in avionics, while the LVDS outputs ease hand-off to modern FPGAs and DACs.
When designing around this part, note that the 52-pin TQFP-EP footprint requires a 4-layer PCB with a continuous ground plane under the exposed pad to meet the stated thermal and EMI performance. Decouple the AVCC and DVCC rails separately with 0.1 µF and 10 µF ceramics placed within 5 mm of each supply pin, and provide a well-bypassed external voltage reference for the best linearity.
This page consolidates distributor stock, MIL-class-V screening documentation, and cross-reference information not found on a single manufacturer datasheet, giving procurement and design engineers a one-stop view of the 5962L0423003VXC for new defense and aerospace programs.
直接替换替代料： 5962L0423003VXC ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
5962L0423003V9A
✅ 直接替换📋 参考替代料（不在目录中）
5962L0423003VYC
✅ 直接替换📋 参考替代料（不在目录中）
AD6645ASTZ
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
AD6644ASTZ-65
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
5962L0423003VXC 最大额定值与电气特性
| Manufacturer | Analog Devices, Inc. |
| Part Status | Active - MIL-PRF-38535 Class V |
| 功能 | Analog-to-Digital Converter (ADC) |
| 分辨率 | 14 bit |
| Sample Rate | 80 MSPS (minimum) |
| Number of Channels | 1 |
| Input Type | Differential analog input |
| Data Interface | Parallel CMOS / LVDS compatible |
| Analog Supply Voltage | 3.3 V or 5 V |
| Digital Supply Voltage | 3.3 V or 5 V |
| 工作温度范围 | -55 °C to +125 °C |
| 封装 / 外壳 | 52-TQFP-EP (52 terminals, exposed pad) |
| 安装类型 | Surface Mount |
| Screening Level | MIL-PRF-38535 Class V |
| SMD / Drawing Number | 5962L0423003VXC |
| Lead Free / RoHS | Per MIL-PRF-38535 Class V configuration - consult datasheet |
| Architecture | Pipeline ADC (multi-stage) |
| MSL Rating | Per MIL-STD-883 Method 2003 |
5962L0423003VXC 52-tqfp-ep (52 terminals, exposed pad) 引脚配置指南
5962L0423003VXC（52-tqfp-ep (52 terminals, exposed pad) 封装）的引脚配置。 该模拟元件具有输入、输出和电源引脚。请参阅制造商数据手册以了解失调调零、补偿和使能引脚配置。适用于信号调理和放大器电路。
暂无详细引脚数据： 5962L0423003VXC.
请参阅 数据手册 以查看完整引脚配置。
典型应用
5962L0423003VXC 适用于 6 应用s: Military Radar IF Sampling, Electronic-Warfare (ECM/ECCM) Receiver, Software-Defined Radio IF Digitizer, Satellite Communications (SATCOM) Modem, High-Temperature Industrial Telemetry, Avionics Signal-Intelligence (SIGINT) Front End.
Military Radar IF Sampling
The 5962L0423003VXC delivers 14-bit resolution at 80 MSPS with MIL-PRF-38535 Class V screening, an exact match for radar IF-sampling chains that must digitize signals above 100 MHz input. In a typical phased-array radar receiver the ADC sits between the down-converting mixer and the FPGA-based pulse compressor, where its 14-bit dynamic range preserves clutter rejection while the Class V screening lets the design pass the radar's full mission-temperature envelope from -55 °C to +125 °C. Wide SFDR across the IF band is the key engineering lever here because it directly bounds the radar's probability of false alarm. Recommended companions: ADL5201 LNA, AD9516 clock generator
推荐
Electronic-Warfare (ECM/ECCM) Receiver
Electronic-warfare receivers must digitize extremely wide instantaneous bandwidths while remaining sensitive to low-amplitude threats, and the 5962L0423003VXC's 14-bit dynamic range plus military temperature envelope fits this requirement exactly. Placed at the IF output of the EW tuner, the ADC drives a downstream FPGA running adaptive digital signal-processing algorithms that classify and jam hostile emitters. The Class V qualification lets the EW receiver meet the airborne platform's qualification program without requalifying the converter. Recommended companions: AD9680 high-speed ADC, AD-FMCOMMS FPGA card
推荐
Software-Defined Radio IF Digitizer
Software-defined radios benefit from placing the ADC as close as possible to the antenna, and the 5962L0423003VXC is well-suited as the IF digitizer in SDRs targeting HF, VHF, and L-band operation. The 14-bit resolution at 80 MSPS captures sufficient bandwidth for narrow-band demodulation while the parallel CMOS/LVDS output simplifies routing into a Zynq-class SoC. The Class V envelope is a strong fit for portable-manpack SDRs that have to operate between -40 °C and +85 °C without re-calibration across that range. Recommended companions: XC7S50-1CSGA324I, ADL5375 modulator
推荐
Satellite Communications (SATCOM) Modem
In SATCOM modems the ADC digitizes the IF chain after the low-noise downconverter, and the 5962L0423003VXC's combination of 14-bit resolution, 80 MSPS, and MIL-class temperature operation is a good match for military SATCOM terminals. Synchronization of the ENCODE clock to a GPS-disciplined reference such as the AD9548 keeps the modem within symbol-rate tolerance across the operational envelope. Wide SFDR protects low-rate QPSK and 16-APSK links against adjacent-channel interference. Recommended companions: AD9548, HMC7044
推荐
High-Temperature Industrial Telemetry
Industrial telemetry in oil-well downhole and turbine-engine environments routinely experiences temperatures above +125 °C, and even though the 5962L0423003VXC's upper limit is +125 °C, its derated margin at high temperature is well characterized by the Class V characterization report. Placed on the downhole data-acquisition board, the ADC samples vibration and pressure sensors at 80 MSPS, with the digital output streamed via LVDS to a microcontroller or FPGA. This application values MIL-class screening less for screening and more for the strict per-lot traceability that comes with it. Recommended companions: ADS127L01, ISO1640
推荐
Avionics Signal-Intelligence (SIGINT) Front End
Avionics SIGINT receivers must digitize dense RF environments where dynamic range directly translates into interception probability, making the 5962L0423003VXC's 14-bit resolution and 80 MSPS attractive. The Class V screening also satisfies the avionics qualification program typically required for flight-clearance. Driving the ADC output into a Zynq SoC for fast-Fourier and demodulation processing lets the SIGINT back-end run real-time channelization at full mission rate. Recommended companions: XC7Z020-1CLG484I, ADC14DS105AISQ/NOPB
推荐
推荐产品汇总
工程参考数据： 5962L0423003VXC ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | 5962L0423003V9A | 5962L0423003VYC | AD6645ASTZ | AD6644ASTZ-65 |
|---|---|---|---|---|---|
| Package | 52-TQFP-EP | 52-TQFP-EP - same | 52-TQFP-EP - same | 52-LQFP-EP - same footprint | 52-LQFP-EP - same footprint |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Sample Rate | 80 MSPS | 80 MSPS | 80 MSPS | 80 MSPS | 65 MSPS (-19%) |
| Screening Level | MIL-PRF-38535 Class V | MIL-PRF-38535 Class V | MIL-PRF-38535 Class V | Commercial | Commercial |
| Operating Temperature | -55 to +125 °C | -55 to +125 °C | -55 to +125 °C | -40 to +85 °C | -40 to +85 °C |
| Pin Count | 52 | 52 | 52 | 52 | 52 |
| Architecture | Pipeline | Pipeline | Pipeline | Pipeline | Pipeline |
| Availability (2026-10-12) | Quote-only (Class V) | Quote-only (Class V) | Quote-only (Class V) | Distributor stock | Distributor stock |
关键差异点
- MIL-PRF-38535 Class V screening with full military temperature envelope （对比 AD6645ASTZ (commercial))
- Guaranteed 80 MSPS minimum sample rate across the military temperature range （对比 AD6644ASTZ-65 (commercial))
- Standardized SMD drawing number for DLA-traceable bills of material （对比 AD6645ASTZ (commercial))
设计说明
The 52-pin TQFP-EP package relies on the exposed pad for low-thermal-resistance heat removal; the EP must be soldered directly to a continuous ground plane with at least 0.5 oz copper. Estimated: with 0.5 oz copper and 9 thermal vias to an inner ground plane, expected theta_JA is around 18 °C/W versus 35 °C/W with no vias, which drops junction rise by ~50 °C at a 1 W internal dissipation. De-rate ADC sample rate if junction temperature approaches +125 °C in a sealed avionics enclosure.
Place one 0.1 µF X7R ceramic within 5 mm of every AVCC pin and a single 10 µF bulk tantalum or polymer cap on each analog rail. Keep the AVCC and DVCC supplies physically separated - use a ferrite bead between the regulator output and AVCC if both are derived from a common rail. Estimated: a 14-bit ADC clocked at 80 MSPS typically draws 250-300 mA on AVCC and 50-80 mA on DVCC; budget for LDO dropout and load-transient response in the regulator selection.
Route the analog differential input (VIN+/-) as a 100 Ω differential pair with matched length within 1 mm to preserve SFDR. Place a balun or transformer coupling immediately at the analog input pins, never after the trace. The ENCODE clock trace must be 50 Ω single-ended and isolated from the analog inputs by at least 4 trace-widths of ground pour. Keep D0-D13 bus traces tightly length-matched (Δt <50 ps) and series-terminated near the ADC outputs.
Do not substitute the commercial AD6645AST for the 5962L0423003VXC on MIL-spec programs - the Class V screening and SMD traceability are contractual requirements and an unauthorized substitution is a counterfeit indicator. Verify the lot's Certificate of Conformance (CoC) and the manufacturer's DLA audit letter before board-level acceptance. If the application is non-military but needs the same electrical performance, AD6645AST in the same 52-LQFP-EP is a lower-cost option without MIL-class screening.
合规信息
5962-prefix SMD parts are governed by MIL-PRF-38535 Class V, which takes precedence over RoHS/REACH commercial compliance regimes. Full compliance status depends on the lead-finish option (/VXC vs /V9A vs /VYC); consult the SMD drawing or the manufacturer's CoC for the program-specific finish. AEC-Q100 is not applicable (this is not an automotive part).
