ADC14DS105AISQ/NOPB - Dual 14-Bit 105 MSPS LVDS ADC
料号： ADC14DS105AISQ/NOPB ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $39.5 | $39.50 |
| 10 | $35.55 | $355.50 |
| 100 | $31.6 | $3,160.00 |
| 500 | $27.97 | $13,985.00 |
| 1,000 | $25.11 | $25,110.00 |
ADC14DS105AISQ/NOPB 概述
An ADC (analog-to-digital converter) translates continuous analog signals into discrete digital codes for processing by FPGAs, DSPs, or microcontrollers. Within the broader taxonomy, the ADC14DS105 sits in the high-speed pipelined ADC family (ADC -> data converter -> signal chain IC -> mixed-signal IC), chosen when both channels and high sample rates are required simultaneously. Pipelined ADCs use a multi-stage architecture with per-stage residue amplification to achieve high conversion rates at moderate resolution, making them well-suited for communications, imaging, and test-and-measurement signal chains.
Key features of the ADC14DS105AISQ/NOPB include dual 14-bit resolution, 105 MSPS per-channel sampling, serial LVDS outputs that minimize pin count and ease PCB routing at high data rates, and selectable internal or external voltage reference. The 60-WQFN package with exposed pad delivers low thermal resistance for sustained high-speed operation, while the serial LVDS interface reduces the FPGA I/O pin count compared to parallel CMOS ADC interfaces.
The device uses a proprietary CMOS pipeline architecture with input S/H (sample-and-hold), multi-bit per stage redundancy for linearity correction, and an on-chip reference. The serialized LVDS interface transmits data on a small number of differential pairs and supports self-test and synchronization features that simplify multi-device synchronization.
Typical applications include communications receivers, multi-channel IF digitizers, medical imaging front-ends, test-and-measurement digitizers, and phased-array radar or beamforming subsystems. The 105 MSPS rate combined with dual channels enables I/Q digitizers and wideband dual-channel acquisition in a single IC.
Designers should note that LVDS routing requires matched-length traces, controlled 100-ohm differential impedance, and AC coupling at the FPGA receiver. Provide adequate local decoupling on AVDD and use a solid ground plane under the exposed pad for stable operation.
This page consolidates manufacturer specifications, distributor pricing, drop-in alternatives and application context not aggregated on the original manufacturer datasheet, providing AEO-optimized information for engineers sourcing dual-channel high-speed ADCs.
直接替换替代料： ADC14DS105AISQ/NOPB ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC14DS105AISQ/NOPB （相同外形与封装尺寸） ——差异在于 Package, Input Type, Number of Channels, Data Interface, Resolution.
快速对比工具——选择替代料号进行并排对比：
ADC14DS105CISQ/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC14DS105AISQE/NOPB
✅ 直接替换✓ 有现货
$44.43 / 个
查看数据手册 →ADC14DS105CISQE/NOPB
✅ 直接替换✓ 有现货
$24.95 / 个
查看数据手册 →ADC14DS105AISQ/NOPB 最大额定值与电气特性
| 分辨率 | 14 bits |
| Number of Channels | 2 (simultaneous sampling) |
| Sampling Rate (per channel) | 105 MSPS |
| Architecture | Pipelined CMOS |
| Input Type | Differential |
| Data Interface | Serial LVDS |
| Number of Inputs | 2 |
| Output Format | Serial LVDS, 2 lanes |
| Voltage Reference | Internal or external (selectable) |
| Sample-and-Hold Ratio | 1:1 |
| 工作温度 | -40C to +85C |
| 封装 | 60-WQFN (9x9 mm) with exposed pad |
| 引脚数量 | 60 |
| 安装类型 | Surface Mount |
| Packaging | Tape & Reel (TR) |
| RoHS 状态 | Compliant |
| Lead Free | Yes |
ADC14DS105AISQ/NOPB 引脚配置
| 引脚 1 | VA1 — Analog supply for channel 1 |
| 引脚 2 | GND — Ground reference |
| 引脚 3 | IN1+ — Channel 1 positive differential input |
| 引脚 4 | IN1- — Channel 1 negative differential input |
| 引脚 5 | VBIAS — Bias voltage (per datasheet) |
| 引脚 6 | GND — Ground reference |
| 引脚 7 | VA1 — Analog supply for channel 1 |
| 引脚 8 | VA2 — Analog supply for channel 2 |
| 引脚 9 | IN2+ — Channel 2 positive differential input |
| 引脚 10 | IN2- — Channel 2 negative differential input |
| 引脚 11 | GND — Ground reference |
| 引脚 12 | VA2 — Analog supply for channel 2 |
| 引脚 13 | VREF — Voltage reference input/output |
| 引脚 14 | GND — Ground reference |
| 引脚 15 | VD — Digital supply |
| 引脚 16 | GND — Ground reference |
| 引脚 17 | TEST — Test mode (per datasheet) |
| 引脚 18 | SYNC — Synchronization input |
| 引脚 19 | CLKP — Differential clock positive |
| 引脚 20 | CLKN — Differential clock negative |
| 引脚 21 | GND — Ground reference |
| 引脚 22 | VD — Digital supply |
| 引脚 23 | OUT1P — Differential LVDS output lane 1 positive |
| 引脚 24 | OUT1N — Differential LVDS output lane 1 negative |
| 引脚 25 | GND — Ground reference |
| 引脚 26 | OUT2P — Differential LVDS output lane 2 positive |
| 引脚 27 | OUT2N — Differential LVDS output lane 2 negative |
| 引脚 28 | GND — Ground reference |
| 引脚 29 | VD — Digital supply |
| 引脚 30 | GND — Ground reference |
| 引脚 31 | DR1P — Data rate clock lane 1 positive (per datasheet) |
| 引脚 32 | DR1N — Data rate clock lane 1 negative |
| 引脚 33 | GND — Ground reference |
| 引脚 34 | DR2P — Data rate clock lane 2 positive |
| 引脚 35 | DR2N — Data rate clock lane 2 negative |
| 引脚 36 | GND — Ground reference |
| 引脚 37 | VD — Digital supply |
| 引脚 38 | GND — Ground reference |
| 引脚 39 | NC — Not connected (per datasheet) |
| 引脚 40 | MODE — Mode selection (per datasheet) |
| 引脚 41 | SDOUT — Serial data output (per datasheet) |
| 引脚 42 | SDEN — Serial data enable |
| 引脚 43 | SCLK — Serial configuration clock |
| 引脚 44 | CSB — Chip select / configuration bar |
| 引脚 45 | VD — Digital supply |
| 引脚 46 | GND — Ground reference |
| 引脚 47 | NC — Not connected (per datasheet) |
| 引脚 48 | NC — Not connected (per datasheet) |
| 引脚 49 | VA1 — Analog supply for channel 1 |
| 引脚 50 | GND — Ground reference |
| 引脚 51 | VA1 — Analog supply for channel 1 |
| 引脚 52 | VA2 — Analog supply for channel 2 |
| 引脚 53 | GND — Ground reference |
| 引脚 54 | VA2 — Analog supply for channel 2 |
| 引脚 55 | GND — Ground reference |
| 引脚 56 | VA2 — Analog supply for channel 2 |
| 引脚 57 | GND — Ground reference |
| 引脚 58 | NC — Not connected (per datasheet) |
| 引脚 59 | NC — Not connected (per datasheet) |
| 引脚 60 | GND — Ground / exposed pad connection |
典型应用
ADC14DS105AISQ/NOPB 适用于 6 应用s: Communications IF / I/Q Digitizer, Test & Measurement Digitizer Front-End, Medical Ultrasound Imaging Front-End, Industrial Multi-Channel Data Acquisition, Software Defined Radio Wideband Front-End, Multi-Channel Wireless Baseband.
Communications IF / I/Q Digitizer
The ADC14DS105AISQ/NOPB is well matched to dual-channel IF digitization in communications receivers. Its 14-bit resolution at 105 MSPS per channel captures the dynamic range needed for demodulating high-order QAM and OFDM waveforms, while the simultaneous sampling on two channels handles I/Q demodulation with minimal channel-to-channel skew. The serial LVDS output streams 14-bit data on a small number of differential pairs, simplifying PCB routing into an FPGA and isolating the analog domain from noisy digital switching.
推荐
Test & Measurement Digitizer Front-End
For broadband oscilloscope and arbitrary waveform digitizer front-ends, the ADC14DS105AISQ/NOPB delivers 14-bit resolution at 105 MSPS per channel in a single IC. Pipelined ADCs in this speed range offer low aperture jitter (typically < 0.5 ps) and excellent SNR, allowing wideband signal capture with good amplitude accuracy. Dual channels are ideal for two-channel scope front-ends; serial LVDS cleanly fans into a Kintex- or Artix-class FPGA for waveform DSP.
推荐
Medical Ultrasound Imaging Front-End
Beamforming and pre-beamform ultrasound digitizers benefit from a low-power dual-channel ADC like the ADC14DS105AISQ/NOPB. Each transducer element captures a 14-bit sample at up to 105 MSPS, and the differential inputs reject common-mode pickup from the analog front-end. Multiple ADC14DS105 devices can be paralleled for higher channel counts, with the serial LVDS digital output reducing channel-to-channel skew during high-density PCB routing in dense probe assemblies.
推荐
Industrial Multi-Channel Data Acquisition
In phased-array radar, sonar and vibration analysis front-ends, the ADC14DS105AISQ/NOPB provides two synchronized 14-bit samples at 105 MSPS in one IC. The differential inputs reject common-mode noise from motors, drives and field cabling, while the pipelined architecture produces consistent latency across channels, which is critical for cross-channel phase calculations. The serial LVDS interface minimizes FPGA pin count per channel and simplifies synchronization across many ADC ICs.
推荐
Software Defined Radio Wideband Front-End
Wideband SDR receivers often need 50-100 MHz of IF bandwidth digitized with good linearity. The ADC14DS105AISQ/NOPB samples two channels at 105 MSPS, providing headroom for direct IF sampling in HF/VHF SDRs and supporting dual-channel diversity receivers. The differential inputs couple cleanly to LNA / mixer stages, while the serialized LVDS output connects directly to Zynq or Kintex-class FPGAs running the demodulation stack in fabric.
推荐
Multi-Channel Wireless Baseband
Multi-radio baseband platforms can place the ADC14DS105AISQ/NOPB on each antenna branch to capture 14-bit, 105 MSPS I/Q streams, supporting diversity or MIMO front-ends. The internal selectable reference simplifies BOM by avoiding a dedicated external reference IC in lower-cost designs, while external reference mode enables multiple ADC14DS105 devices to share a system clock for coherent sampling across RF chains.
推荐
推荐产品汇总
工程参考数据： ADC14DS105AISQ/NOPB ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC14DS105CISQ/NOPB | ADC14DS105AISQE/NOPB | ADC14DS105CISQE/NOPB |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 60-WQFN (9x9) | 60-WQFN (9x9) - same | 60-WQFN (9x9) - same | 60-WQFN (9x9) - same |
| Resolution | 14 bits | 14 bits | 14 bits | 14 bits |
| Number of Channels | 2 (simultaneous) | 2 | 2 | 2 |
| Sampling Rate | 105 MSPS / channel | 105 MSPS | 105 MSPS | 105 MSPS |
| Performance Grade | Grade A (tight SFDR/ENOB) | Grade C | Grade A | Grade C |
| Data Interface | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| RoHS | Compliant | Compliant | Compliant | Compliant |
| Packaging | Tape & Reel (TR) | Tape & Reel | Tape & Reel | Tape & Reel |
关键差异点
- Grade A bin for tight linearity and noise performance （对比 ADC14DS105CISQ/NOPB)
- Identical die, distinct reel code (E suffix) （对比 ADC14DS105AISQE/NOPB)
- Full 14-bit resolution at the rated 105 MSPS per channel （对比 ADC14DS105CISQE/NOPB)
设计说明
LVDS clock and data lines must be routed as 100-ohm differential pairs with matched lengths within the tolerance given in the datasheet (typically < 150 mils skew lane-to-lane). Keep LVDS pairs over a continuous ground reference plane and away from noisy supplies; insert AC-coupling capacitors close to the receiver if the FPGA supply differs from the ADC's LVDS common-mode range. This preserves the SFDR margins of the Grade A bin.
Estimated: at 105 MSPS per channel with VA = 1.8 V and VD = 1.8 V, the ADC14DS105 family draws on the order of 350-500 mW total. Use Pi-style filtering (small ferrite + bulk + decoupling cap) on each supply rail, with 0.1 uF X7R + 10 uF bulk ceramics placed within 5 mm of each supply pin. Star-route analog ground (GND pins and exposed pad) back to a quiet ground pour separate from the digital return. Estimated based on datasheet typical supply currents and should be re-derived from the manufacturer's electrical characteristics table for the exact operating conditions.
Do not operate the exposed pad without soldering it to the PCB ground/power plane; thermal rise and latch-up risk both increase. Do not drive the differential clock with a single-ended source unless an LVDS driver is interposed; the converter's aperture jitter is highly sensitive to clock phase noise, so use a low-jitter clock like an LMK device or a high-Q crystal.
Place the input coupling network (typically a transformer or fully differential op-amp driver) close to INx+/INx- to limit the analog bandwidth at the ADC input. Apply proper termination (commonly 100-ohm differential or per the recommended evaluation board schematic) to avoid reflections that manifest as spurs in the FFT output.
合规信息
RoHS compliant per TI / DigiKey product pages; commercial-grade (not AEC-Q100) ADC; identical-pin same-package variants (CISQ, AISQE, CISQE) are also RoHS compliant.
