5M80ZE64C5N - MAX V CPLD 64-Macrocell 118.3 MHz 64-EQFP | Intel
料号： 5M80ZE64C5N ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $7.45 | $7.45 |
| 10 | $6.78 | $67.80 |
| 100 | $5.92 | $592.00 |
| 500 | $5.1 | $2,550.00 |
| 1,000 | $4.38 | $4,380.00 |
5M80ZE64C5N 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile, low-density programmable logic device that combines multiple PAL-like macrocell blocks with a programmable interconnect matrix. In the broader taxonomy, a CPLD sits below an FPGA in density but offers deterministic timing, predictable propagation delays, and instant-on operation, making it ideal for glue logic, I/O expansion, bus bridging, and power-up sequencing. The MAX V family specifically targets low-power applications where battery life, board area, and design simplicity are critical.
Key features include 4.5 ns maximum global clock setup time, IEEE 1149.1 JTAG boundary-scan support, an internal oscillator, programmable LVTTL/LVCMOS I/O standards at 1.5 V, 1.8 V, 2.5 V, and 3.3 V, and built-in flash configuration storage. The 64-pin EQFP package provides 54 usable I/Os plus an exposed bottom pad that must be soldered to the PCB ground plane for electrical connectivity and mechanical stability.
The 5M80ZE64C5N architecture is a classic AND-OR PLA-style fabric with JTAG-based in-system programmability. Its flash configuration cells retain bitstream data without a battery, eliminating boot PROM cost and BOM. Compared to the earlier MAX II family, MAX V offers higher macro density and lower static power, while remaining compatible with the Quartus II / Intel Quartus Prime design flow, enabling portable IP reuse across MAX generations.
Typical applications include I/O expansion and bus bridging in industrial controllers, power-up sequencing logic in multi-rail systems, glue logic in networking line cards, and feature-enabling logic in low-cost consumer electronics. The combination of instant-on, low power, and small footprint also makes the part suitable for battery-powered portable devices and automotive body modules where deterministic start-up behavior is required.
When designing with the E64 package, engineers must connect the exposed bottom pad to the ground plane to meet datasheet electrical and mechanical requirements. Designers should also note I/O bank voltage constraints and use external level shifters when interfacing mixed-voltage rails. The device is non-volatile, so no configuration download step is needed at power-up.
This page synthesizes live distributor pricing, drop-in alternatives within the MAX V family, and practical design notes - information gain that complements the official Intel MAX V Device Handbook.
直接替换替代料： 5M80ZE64C5N ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： 5M80ZE64C5N （相同外形与封装尺寸） ——差异在于 Package, Programming Interface, Operating Temperature, Configuration Memory, Logic Elements (LE).
快速对比工具——选择替代料号进行并排对比：
5M80ZE64I5N
✅ 直接替换✓ 有现货
$4.1 / 个
查看数据手册 →5M80ZE64C5
✅ 直接替换📋 参考替代料（不在目录中）
5M160ZE64C5N
✅ 直接替换✓ 有现货
$4.95 / 个
查看数据手册 →5M40ZE64C5N
✅ 直接替换✓ 有现货
$4.85 / 个
查看数据手册 →5M80ZE64C5N 最大额定值与电气特性
| Family | MAX V |
| Device Type | CPLD - Complex Programmable Logic Device |
| Number of Macrocells | 64 |
| Number of Logic Elements | 80 |
| Number of User I/Os | 54 |
| Maximum Internal Frequency | 118.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns |
| Global Clock Setup Time | 4.5 ns max |
| Core Supply Voltage | 1.8 V |
| I/O Standards Supported | LVTTL, LVCMOS (1.5 V, 1.8 V, 2.5 V, 3.3 V) |
| Configuration Memory | Non-volatile flash |
| Programming Interface | JTAG (IEEE 1149.1) |
| 封装 | 64-EQFP (7x7 mm) with exposed pad |
| 工作温度范围 | 0C to +85C (TJ) |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
| 无卤 | Yes |
5M80ZE64C5N 引脚配置
| 引脚 1 | I/O — User I/O pin (bank 1) |
| 引脚 2 | I/O — User I/O pin (bank 1) |
| 引脚 3 | I/O — User I/O pin (bank 1) |
| 引脚 4 | I/O — User I/O pin (bank 1) |
| 引脚 5 | I/O — User I/O pin (bank 1) |
| 引脚 6 | I/O — User I/O pin (bank 1) |
| 引脚 7 | I/O — User I/O pin (bank 1) |
| 引脚 8 | VCCIO1 — I/O bank 1 supply voltage |
| 引脚 9 | I/O — User I/O pin (bank 1) |
| 引脚 10 | I/O — User I/O pin (bank 1) |
| 引脚 11 | GND — Ground |
| 引脚 12 | I/O — User I/O pin (bank 2) |
| 引脚 13 | I/O — User I/O pin (bank 2) |
| 引脚 14 | I/O — User I/O pin (bank 2) |
| 引脚 15 | I/O — User I/O pin (bank 2) |
| 引脚 16 | I/O — User I/O pin (bank 2) |
| 引脚 17 | I/O — User I/O pin (bank 2) |
| 引脚 18 | I/O — User I/O pin (bank 2) |
| 引脚 19 | VCCIO2 — I/O bank 2 supply voltage |
| 引脚 20 | I/O — User I/O pin (bank 2) |
| 引脚 21 | I/O — User I/O pin (bank 2) |
| 引脚 22 | GND — Ground |
| 引脚 23 | I/O — User I/O pin (bank 3) |
| 引脚 24 | I/O — User I/O pin (bank 3) |
| 引脚 25 | I/O — User I/O pin (bank 3) |
| 引脚 26 | I/O — User I/O pin (bank 3) |
| 引脚 27 | I/O — User I/O pin (bank 3) |
| 引脚 28 | I/O — User I/O pin (bank 3) |
| 引脚 29 | VCCIO3 — I/O bank 3 supply voltage |
| 引脚 30 | I/O — User I/O pin (bank 3) |
| 引脚 31 | I/O — User I/O pin (bank 3) |
| 引脚 32 | GND — Ground |
| 引脚 33 | I/O — User I/O pin (bank 4) |
| 引脚 34 | I/O — User I/O pin (bank 4) |
| 引脚 35 | I/O — User I/O pin (bank 4) |
| 引脚 36 | I/O — User I/O pin (bank 4) |
| 引脚 37 | I/O — User I/O pin (bank 4) |
| 引脚 38 | I/O — User I/O pin (bank 4) |
| 引脚 39 | VCCIO4 — I/O bank 4 supply voltage |
| 引脚 40 | I/O — User I/O pin (bank 4) |
| 引脚 41 | I/O — User I/O pin (bank 4) |
| 引脚 42 | GND — Ground |
| 引脚 43 | TDI — JTAG test data input |
| 引脚 44 | TMS — JTAG test mode select |
| 引脚 45 | TCK — JTAG test clock |
| 引脚 46 | TDO — JTAG test data output |
| 引脚 47 | nSTATUS — Configuration status (open-drain) |
| 引脚 48 | nCONFIG — Configuration control input |
| 引脚 49 | CONF_DONE — Configuration complete (open-drain) |
| 引脚 50 | DEV_CLRn — Device-wide clear (active low) |
| 引脚 51 | DEV_OE — Device-wide output enable |
| 引脚 52 | GND — Ground |
| 引脚 53 | VCCINT — Core supply voltage (1.8 V) |
| 引脚 54 | I/O — User I/O pin (bank 1) |
| 引脚 55 | I/O — User I/O pin (bank 1) |
| 引脚 56 | I/O — User I/O pin (bank 1) |
| 引脚 57 | I/O — User I/O pin (bank 1) |
| 引脚 58 | I/O — User I/O pin (bank 1) |
| 引脚 59 | I/O — User I/O pin (bank 1) |
| 引脚 60 | I/O — User I/O pin (bank 1) |
| 引脚 61 | VCCIO1 — I/O bank 1 supply voltage |
| 引脚 62 | I/O — User I/O pin (bank 1) |
| 引脚 63 | I/O — User I/O pin (bank 1) |
| 引脚 64 | I/O — User I/O pin (bank 1) |
| 引脚 EP | GND (EP) — Exposed pad - must be soldered to PCB ground plane |
典型应用
5M80ZE64C5N 适用于 7 应用s: Industrial I/O Expansion and Bus Bridging, Power-Up Sequencing in Multi-Rail Systems, Networking Line Card Glue Logic, Consumer Electronics Feature Logic, Battery-Powered Portable Device Control, Automotive Body Electronics and Infotainment Modules, Legacy Board Replacement and Obsolescence Bridging.
Industrial I/O Expansion and Bus Bridging
The 5M80ZE64C5N excels at I/O expansion and bus bridging in industrial controllers where deterministic timing and instant-on behavior are required. Its 64 macrocells provide sufficient logic capacity to translate between SPI, I2C, UART, and parallel interfaces without external glue logic. The 7.5 ns pin-to-pin propagation delay ensures consistent bus-cycle latency, while the non-volatile flash memory eliminates boot time at power-up - critical for PLCs and HMI panels that must respond to operator input within milliseconds of power-on. The 64-EQFP footprint fits within 7x7 mm, simplifying layout on densely populated industrial controller boards.
推荐
Power-Up Sequencing in Multi-Rail Systems
The 5M80ZE64C5N is widely used to implement power-up and power-down sequencing logic in multi-rail systems such as servers, networking switches, and FPGA-based boards. Its 80 logic elements and 54 user I/Os can monitor PG (power-good) signals from multiple DC-DC converters and assert enable signals in the correct order. The 1.8 V core supply and 3.3 V-tolerant I/O banks simplify interface with modern POL regulators. Because the device is non-volatile, the sequencing state machine is active the moment power rails stabilize, with no firmware boot delay.
推荐
Networking Line Card Glue Logic
In networking line cards, the 5M80ZE64C5N serves as a flexible glue-logic layer between PHY chips, MACs, FPGAs, and switch fabrics. Its JTAG-based ISP (in-system programmability) allows late-stage design changes via boundary-scan without board rework. The 118.3 MHz maximum frequency supports gigabit Ethernet sideband signaling and MDIO/MDC interfaces, while the 64-EQFP exposed-pad package provides the mechanical robustness required for high-vibration telecom environments. The low static power of the MAX V family is also beneficial for thermally constrained line-card designs.
推荐
Consumer Electronics Feature Logic
The 5M80ZE64C5N is an excellent fit for consumer products such as set-top boxes, smart-home hubs, and small appliances that need a few dozen logic functions without paying for an FPGA. Its low unit cost at high volumes, combined with the Quartus Prime Lite free design toolchain, makes it attractive for cost-sensitive consumer designs. Instant-on behavior means the part can wake up the rest of the system and handshake with display or sensor subsystems the moment power is applied, eliminating perceived boot lag. The compact 7x7 mm EQFP footprint also simplifies single-sided PCB layouts.
推荐
Battery-Powered Portable Device Control
The MAX V family's low static power makes the 5M80ZE64C5N suitable for battery-powered portable devices such as handheld instruments, IoT edge nodes, and wearable accessories. The 1.8 V core supply draws minimal quiescent current, while flash configuration eliminates the inrush surge of an FPGA boot sequence. The device can implement low-duty-cycle sensor wake-up logic, button-debounce circuits, and LED drivers in a single 7x7 mm package, freeing the main microcontroller from repetitive interrupt service routines. The 0C to +85C operating range covers typical consumer portable environments.
推荐
Automotive Body Electronics and Infotainment Modules
The 5M80ZE64C5N is used in non-safety automotive body modules such as infotainment, instrument cluster backlight drivers, and HVAC control panels where its 0C to +85C operating range and non-volatile configuration are valuable. It can implement CAN bus wake-up logic, body-control message routing, and display-matrix scanning with deterministic 7.5 ns timing. For under-hood or AEC-Q100-mandated applications, however, designers should select the MAX V 'A' grade variants or an automotive-qualified CPLD family, since the standard 5M80ZE64C5N is not AEC-Q100 certified.
推荐
Legacy Board Replacement and Obsolescence Bridging
The 5M80ZE64C5N serves as a modern, active-lifecycle replacement for end-of-life CPLDs in legacy industrial, telecom, and test equipment designs. Designers migrating from the older MAX 7000 or MAX II families can port designs to MAX V using the same Quartus Prime toolchain with minimal code changes, while gaining flash non-volatility and lower power. With a documented EOL horizon around 2026 per industry sources, engineers planning long-life-cycle systems should consider the higher-density MAX V siblings (5M160Z, 5M240Z) or monitor Intel's product roadmap for continued MAX V supply.
推荐
推荐产品汇总
工程参考数据： 5M80ZE64C5N ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | 5M80ZE64I5N | 5M80ZE64C5 | 5M160ZE64C5N | 5M40ZE64C5N |
|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Package | 64-EQFP (7x7) | 64-EQFP (7x7) - same | 64-EQFP (7x7) - same | 64-EQFP (7x7) - same | 64-EQFP (7x7) - same |
| Macrocells | 64 | 64 | 64 | 160 | 40 |
| Logic Elements | 80 | 80 | 80 | 160 | 40 |
| Maximum Frequency | 118.3 MHz | 118.3 MHz | 118.3 MHz | 118.3 MHz | 118.3 MHz |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 7.5 ns | 7.5 ns | 7.5 ns | 7.5 ns |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | 0C to +85C (Commercial) | -40C to +100C (Industrial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
| User I/Os | 54 | 54 | 54 | 54 | 54 |
关键差异点
- Non-volatile flash configuration with instant-on behavior （对比 SRAM-based small FPGAs)
- Lowest static power in the 64-macroclass MAX V family （对比 MAX II EPM570F100C5N)
- Wide I/O voltage support on each bank （对比 5M160ZE64C5N (same family, higher density))
设计说明
The 64-EQFP package includes a central exposed pad (pin EP) that MUST be soldered to the PCB ground plane. Use an array of thermal vias (typically 9-16 vias in a 3x3 or 4x4 pattern) directly under the EP to provide a low-impedance ground path and to meet the datasheet's mechanical mounting requirements. The EP serves electrical grounding and mechanical stability - not primarily thermal dissipation for this low-power CPLD.
The 5M80ZE64C5N requires two supply rails: VCCINT at 1.8 V for the core logic and VCCIO1/VCCIO2/VCCIO3/VCCIO4 for each I/O bank. Decouple each VCCINT and VCCIO pin with a 0.1 uF ceramic capacitor placed within 2-3 mm of the package pin, plus a bulk 10 uF tantalum or ceramic capacitor near the device. Bank voltages can be mixed (1.5 V, 1.8 V, 2.5 V, or 3.3 V) but each bank must be tied to a single rail - level shifting between banks requires external circuitry.
Do not assume the 5M80ZE64C5N is pin-compatible with MAX II CPLDs in the same E64 package - while pin counts match, several power and JTAG pins are reassigned between MAX II and MAX V. Always re-import the MAX V pinout file into your Quartus Prime project. Also note that the device is non-volatile, so design changes require JTAG re-programming; budget 3-5 seconds for ISP via JTAG during production.
Keep JTAG signals (TDI, TMS, TCK, TDO) routed with short, parallel traces and a ground reference to minimize noise coupling. The nSTATUS, nCONFIG, and CONF_DONE signals are open-drain and require external pull-up resistors (typically 4.7 kohm to 10 kohm) to VCCIO. Place these pull-ups close to the CPLD, not at the programming header, to ensure clean ISP operation.
合规信息
RoHS compliant and halogen-free per the manufacturer datasheet and GlobalSpec listing. Not AEC-Q100 qualified - use MAX V 'A' grade variants or dedicated automotive CPLDs for AEC-Q100 applications.
